www.geehy.com Page 46
Field
Name
R/W
Description
15:8
WAITx
R/W
Attribute Memory x Wait Time Configure
This bit takes HCLK as the clock cycle and defines the minimum
hold time of the command. After the defined time, if the waiting
signal is effective low, the hold time of the command will become
longer.
0000 0000: Reserved
0000 0001: 2 HCLK wait cycle introduced by deasserting
NWAIT)
0000 0010: 3 HCLK cycles
……
1111 1110: 255 HCLK wait cycle introduced by
deasserting NWAIT)
1111 1111: Reserved
23:16
HLDx
R/W
Attribute Memory x Hold Time Configure
This bit takes CLK as the clock cycle, and defines the hold time of
address signal after sending the command.
0000 0000: Reserved
0000 0001: 1 HCLK cycle for write accesses, 3 HCLK cycles for
read accesses
0000 0010: 2 HCLK cycles
……
1111 1110: 254 HCLK cycles for write accesses, 256 HCLK cycles
for read accesses
1111 1111: Reserved
31:24
HIZx
R/W
Attribute Memory x Databus Hiz Time Configure
This bit takes HCLK as the clock cycle and defines the time of high-
impedance state of data bus, which is only effective for write
operation.
0000 0000: 0 HCLK cycle
0000 0001: 1 HCLK cycle
……
1111 1111: 255 HCLK cycles
I/O space timing register 4 (SMC_IOSTIM4)
Offset address: 0xB0
Reset value: 0xFCFC FCFC
Field
Name
R/W
Description
7:0
SET
R/W
I/O x Setup Time Configure
This bit takes CLK as the clock cycle, and defines the time of setting up
the address signal before sending the command.
0000 0000: 1 HCLK cycle
0000 0001: 2 HCLK cycles
……
1111 1111: 256 HCLK cycles
