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DS_Readwait waits for "read wait stop" command
1. "Read wait stop" is enabled
DS_WaitR
2. DPSM is turned off
DS_Idle
APB2 interface
APB2 interface realizes access to SDIO register, data FIFO and generation of
interrupt and DMA request. It includes data FIFO unit, register unit and
interrupt/DMA request control logic.
SDIO interrupt
When at least one of the selected state flags is high, the interrupt logic will
generate an interrupt request. Interrupt enable register enables the interrupt
logic to generate corresponding interrupt.
Data FIFO
The data FIFO unit has a data buffer area for receive and transmit FIFO. FIFO
includes a data buffer with 32-bit width for each word and with depth of 32
words. The transmit FIFO is used when data needs to be written to the card; the
data to be transmitted is written to the transmit FIFO through APB2 bus, and the
data unit in SDIO adapter reads data from the transmit FIFO and then transmits
the data to the card. The receive FIFO is used to read data from the card, and
then write the data to be transmitted to the receive FIFO.
Register unit
The register unit includes all system registers and generates signals for
communication between the control card and the controller.
Card Function Description
Card register
The card internally defines the interface registers: OCR, CID, CSD, EXT_CSD,
RCA, DSR and SCR. These registers can access only through corresponding
commands. OCR, CID, CSD and SCR registers include the specific information
of the card. RCA and DSR registers are configuration registers for storing the
actual configuration parameters. EXT_CSD register includes both the specific
information of the card and the actual structure parameters.
OCR register: 32-bit operating condition register stores V
DD
voltage description
and memory mode indication (MMC) of the card. In addition, the register
includes a state information bit. If the card power-on process has been
completed, this state bit will be set. This register is slightly different between
