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Field
Name
R/W
Description
31
OWN
R/W
Own
0: This describer belongs to CPU
1: This describer belongs to DMA
DMA will clear this bit when the frame transmission is completed or the
buffer allocated in the descriptor is empty. All bits of the first descriptor
of this frame should be set after all subsequent descriptors belonging
to the same frame are set.
Transmit descriptor word 1 (TXDES1)
Field
Name
R/W
Description
12:0
TXBS1
R/W
Transmit Buffer 1 Size
These bits indicate the size of the first data buffer. If the bit is 0, DMA will
ignore this buffer and use the buffer 2 or the next descriptor, depending
on the value of TXDES0[20].
15:13
Reserved
28:16
TXBS2
R/W
Transmit Buffer 2 Size
These bits indicate the size of the second data buffer in bytes. If
TXDES0[20]=1, this field will be invalid.
31:29
Reserved
Transmit descriptor word 2 (TXDES2)
Field
Name
R/W
Description
31:0
TXADDR1_TXFTSL R/W
Transmit Buffer 1 Address Pointer / Transmit frame timestamp
low
It indicates the location of the data in the memory to the DMA.
When all data have been transmitted, the DMA can use these
bits to return the timestamp data.
TXADDR1: When TXDES0[31]=1, these bits indicate the
physical address of buffer 1. There are no restrictions on
buffer address alignment.
TXFTSL: Before TXDES0[31] is cleared to zero, the DMA will
update this field with the 32 least significant bits of the
timestamp captured for the corresponding transmitted frame.
The bit field contains a timestamp only when the timestamp
function of this frame is activated and LS=1.
Transmit descriptor word 3 (TXDES3)
