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Table 25 Programmable NAND/PC Card Timing Parameters
Parameter
Function
Operation
mode
Unit
Minimum
Maximum
Memory data
bus high-
impedance
time
The time of holding the data
bus in high-impedance state
after starting write operation
Write
AHB clock
cycle
(HCLK)
0
255
Memory hold
time
The number of clocks
holding the address after
transmitting the command,
also the hold time of data
during write operation
Read/Write
1
254
Memory
waiting time
Minimum transmitting
duration
2
256
Memory setup
time
The number of clocks that
set up the address before
issuing the command
1
255
SMC register address mapping
Table 26 SMC Register Address Mapping
Register name
Description
Offset address
SMC_CSCTRL1…4
SRAM/NOR flash memory chip selection
control register 1…4
8*(x-1),x=1…4
SMC_CSTIM1…4
SRAM/NOR flash memory chip selection
timing register 1…4
0x04 + 8*(x-1),x=1…4
SMC_WRTTIM1…4
SRAM/NOR flash memory write timing
register 1…4
0x104 + 8*(x-1),x=1…4
SMC_CTRL2…4
PC card/NAND flash memory control
register 2…4
0x40 + 0x20 * (x-1),x=2…4
SMC_STSINT2…4
FIFO state and interrupt register 2…4
0x44 + 0x20 * (x-1),x=2…4
SMC_CMSTIM2…4
General-purpose memory space timing
register 2...4
0x48 + 0x20 * (x-1),x=2…4
SMC_AMSTIM2…4
Attribute memory space timing register
2...4
0x4C + 0x20 * (x-1),x=2…4
SMC_IOSTIM4
I/O space timing register 4
0XB0
SMC_ECCRS2/3
ECC result register 2/3
0x54 + 0x20 * (x-1), x=2 or 3
