www.geehy.com Page 530
Reset value: 0x0000 0080
Read this register when ONEP bit of OTG_HS1_GCINT register is set to 1;
Read OTG_HS1_DAEPINT register to obtain the accurate endpoint number of
the device endpoint x interrupt register, and then read the register; only when
the corresponding bit of the register is cleared to 0, can the corresponding bit of
OTG_HS1_DAEPINT register and OTG_HS1_GCINT register be cleared to 0.
Field
Name
R/W
Description
0
TSFCMP
RC_W1
Transfer Complete Interrupt
This bit indicates that the transmission on the endpoint has
been completed.
1
EPDIS
RC_W1
Endpoint Interrupt Disable
This bit means that the endpoint is disabled.
2
Reserved
3
TO
RC_W1
Timeout Interrupt
This bit is only applicable to the control IN endpoints,
indicating that the response to the recently received IN
token has timed out.
4
ITXEMP
RC_W1
Receive IN Token Interrupt when FIFO is empty
This bit is only applicable to non-periodic IN endpoints,
indicating that IN token is received when the corresponding
TXFIFO of the endpoint is empty.
5
Reserved
6
IEPNAKE
RC_W1
IN Endpoint NAK Effective
This bit indicates that the module samples NAK, namely, the
NAK bit of the IN endpoint has taken effect.
This bit will be cleared to 0 when NAKCLR bit of
OTG_HS1_DIEPCTRLx register is written.
7
TXFE
R
TXFIFO Empty Interrupt
An interrupt will be generated when TXFIFO of this endpoint
is empty.
8
TXFUDR
TXFIFO Underrun
An interrupt will be generated when TXFIFO underrun is
detected.
9
BUFFNA
Buffer Not Available Interrupt
When the descriptor cannot be processed by the module,
the buffer is unavailable, and an interrupt will be generated.
10
Reserved
11
PDROFLG
Packet Dropped Flag
This bit indicates that an ISOC OUT data packet is
discarded without interrupt.
12
BERR
Babble Error Interrupt
13
NAK
NAK Interrupt
This interrupt can be generated in two situations:
The device transmits/receives NAK
The synchronous IN endpoint transmits the data
packet with 0 length
