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Table 144 TX Interface Signal Encoding
MII_TX_EN
MII_TXD [3:0]
Description
0
0000-1111
Normal frame internal
1
0000-1111
Normal data transmission
Table 145 RX Interface Signal Encoding
MII_RX_DV
MII_RX_ER
MII_RXD [3:0]
Description
0
0
0000-1111
Normal frame internal
0
1
0000
Normal frame internal
0
1
0001-1101
Reserved
0
1
1110
Error carrier detection
0
1
1111
Reserved
1
0
0000-1111
Normal data receiving
1
1
0000-1111
Data receiving error
MII clock source
TX_CLK and RX_CLK clock signal can take effect only when 25MHz clock is
provided to external PHY, and this signal can be output through MCO pin. The
required frequency can be obtained on MCO pin through 25 MHz external
quartz crystal only when PLL frequency doubling is configured.
Reduced media independent interface (RMII)
RMII reduces the number of pins of MCU of Ethernet peripherals and external
PHY at 10/100Mbit/s. According to IEEE 802.3u standard, MII has 16 data and
control signal pins. RMII reduces the number of pins to 7.
RMII is instantiated between MAC and PHY. It is conductive to converting MII of
MAC to RMII. RMII has the following characteristics:
Separate 2-bit wide transmitting and receiving data path
10-Mbit/s and 100-Mbit/s running speed
The reference clock is 50MHz
Provide the same reference clock to MAC and external Ethernet PHY
from the outside
RMII clock source
Use external 50MHz clock or embedded PLL to generate 50MHz-frequency
signal to drive PHY.
