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SMC signal name
Signal direction
Function
NL
（
=NADV
）
Output
Effective address signal
NBL[1]
Output
High byte enable
NBL[0]
Output
Low byte enable
Note: The output signal of the controller changes at the rising edge of the internal clock; in the
synchronous write mode, the output data changes at the falling edge of the memory clock.
NOR Flash/PSRAM controller provides programmable timing parameters for
external memory, including the parameters in the following table:
Table 20 Programmable NOR/PSRAM Timing Parameters
Parameter
Function
Access mode
Unit
Minimum
Maximum
Data
generation
time
The number of
clocks required to
generate the first
data in burst mode
Synchronous
Memory clock
cycle (CLK)
2
17
Clock division
factor
The ratio of memory
access clock cycle
(CLK) to AHB clock
cycle
Synchronous
AHB clock cycle
(HCLK)
2
16
Bus recovery
time
Duration of Bus
recovery phase
Asynchronous
or
synchronous
read
1
16
Data setup
time
Duration of data
setup phase
Asynchronous
2
256
Address hold
time
Duration of address
hold phase
Synchronous,
multiplexing
IO
2
16
Address
setup time
Duration of address
setup phase
Asynchronous
1
16
NAND flash memory and PC card
Address mapping
Memory blocks 2, 3 and 4 are used to access NAND flash memory and PC
card. Each memory block is also divided into different areas, the corresponding
effect of different areas is different, and the specific distribution is as follows:
Table 21 Address Mapping of Memory Blocks 2 3 and 4
SMC memory block
Storage space
Start address
End address
Memory block 2-NAND
flash memory
General
0x70000000
0x73FFFFFF
Attributes
0x78000000
0x7BFFFFFF
