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High-speed OTG USB configuration register
(OTG_HS1_GUSBCFG)
Offset address: 0x0C
Reset value: 0x0000 0A00
Field
Name
R/W
Description
2:0
SEFLG
R/W
FS Timeout Calibration
The additional delay of PHY includes the number of PHY clocks
and FS timeout interval. The status of data line may be different
for different PHY..
The timeout value of OTG_FS is 16~18-bit time.
5:3
Reserved
6
FSSTSEL
W
Full-Speed Serial Transceiver Select
0: USB2.0 high-speed ULPI PHY
1: USB1.1 full-speed serial transceiver
7
Reserved
8
SRPEN
R/W
SRP Enable
0: Disable
1: Enable
If the SRP function is disabled, connecting the device cannot be
requested to activate V
BUS
and the session cannot be started.
9
HNPEN
R/W
HNP Enable
0: Disable
1: Enable
13:10
TRTIM
R/W
USB Turnaround Time
f
PHYCLK
=48MHZ, in f
PHYCLK
. The clock frequency of AHB is at least
30MHz.
TRTIM=4×f
AHBCLK
+f
PHYCLK
Example:
When f
AHBCLK
=72MHz, TRTIM will be set to 7.
14
Reserved
15
PHYLPSEL
R/W
PHY Low-Power Select
0: Internal PLL clock 480MHz
1: External clock 48MHz
Generally, 48MHz clock is used. In 480MHz clock mode, UTMI
interface runs at 60 (8-bit data) or 30MHz (16 bit data); in 48MHz
mode, run at 48MHz.
16
Reserved
17
ULPISEL
R/W
ULPI PHY Interface Select
0: ULPI interface
1: ULPI FS/LS serial interface
This bit is valid only when FS serial transceiver is selected on
ULPI PHY.
