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MSB is always the first in the data direction
Transmitting and receiving supports DMA function
SPI functional description
Description of SPI signal line
Table 99 SPI Signal Line Description
Pin name
Description
SCK
Master device: SPI clock outputs
Slave device: SPI clock inputs
MISO
Master device: Input the pin and receive data
Slave device: Output the pin and transmit data
Data direction: From slave device to master device
MOSI
Master device: Output the pin and transmit data
Slave device: Input the pin and receive data
Data direction: From master device to slave device
NSS
Software NSS mode: NSS pin can be used for other purposes.
NSS mode of master device hardware: NSS output, single master mode.
NSS closed output: Operation of multiple master environments is allowed.
NSS mode of slave device hardware: NSS signal is set to low level as chip selection
signal of slave.
Phase and polarity of clock signal
The clock polarity and clock phase are CPOL and CPHA bits of SPI_CTRL1
register.
Clock polarity CPOL means the level signal of SCK signal line when SPI is in
idle state.
When CPOL=0, SCK signal line is in idle state and at low level
When CPOL=1, SCK signal line is in idle state and at high level
Clock phase CPHA means the sampling moment of data
When CPHA=0, the signal on MOSI or MISO data line will be sampled
by the "odd edge" on SCK clock line.
When CPHA=1, the signal on MOSI or MISO data line will be sampled
by the "even edge" on SCK clock line.
SPI can be divided into four modes according to the states of clock phase
CPHA and clock polarity CPOL.
Table 100 Four Modes of SPI
SPI mode
CPHA
CPOL
Sampling moment
Idle SCK clock
0
0
0
Odd edge
Low level
1
0
1
Odd edge
High level
