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resources. Only one of two USB OTG_HS can be used at the same time. Their difference is:
one has on-chip UTMI USB PHY (there is internal PLL with 60MHz output), while the other
does not have.
Memory mapping
The assigned addresses of memory mapping include the core (including core
peripherals), on-chip Flash (including main memory area, system memory area
and option bytes), on-chip SRAM, and bus peripherals (including AHB and APB
peripherals). Please refer to the data manual of the corresponding model for
specific information of various addresses.
Embedded SRAM
The product has backup SRAM (4KB) and system SRAM (192KB). The system
SRAM is divided into three parts: SRAM1 (112KB), SRAM2 (16KB) and CCM
(64KB).
SRAM1 and SRAM2
The main SRAM1 and auxiliary SRAM2 can be accessed by byte, half word (16
bits) or full word (32 bits). The mapping address of SRAM1 and SRAM2 is
0x2000 0000, and the main module can be accessoed by all AHB.
Core couple memory (CCM)
The mapping address of CCM (64KB) is 0x1000 0000, and it can only be
accessed by CPU through D-bus.
Bit band
Arm
®
Cortex
®
-M4 memory is mapped with two bit-band areas, and it maps each
word in the alias memory area to one bit in the bit-band memory. Write a word to
the alias memory and there will be the same effect as the read-change-write
operation on the target of the bit-band area. Both peripheral register and SRAM
are mapped into a bit band area, and it is allowed to perform single bit-band
write and read operations.
The following gives a mapping formula:
bit_word_addr=bit_ba
（
byte_offset×32
）
+
（
bit_number×4
）
Startup configuration
APM32F4xx series MCU realizes a special mechanism. By configuring the
BOOT[1:0] pin, there are three different startup modes, and the system can not
only start from Flash memory or system memory, but also start from the built-in
SRAM. The memory selected as the start zone is determined by the selected
