www.geehy.com Page 497
Field
Name
R/W
Description
18
ULPIAR
R/W
ULPI Auto-Resume
This bit indicates whether ULPI PHY supports auto-resume
function.
0: Not supported
1: Supported
19
ULPICLKP
R/W
ULPI Clock Power
This bit indicates whether internal clock power supply is turned off
when PHY is suspended.
0: Open
1: Not off
20
ULPIEVDSEL
R/W
ULPI External V
BUS
Drive Select
Through this bit, ULPI PHY selects to drive V
BUS
by internal or
external power supply.
0: Internal charge pump
1: External power supply
21
ULPIEVC
R/W
ULPI External V
BUS
Compare
Through this bit, ULPI PHY selects internal or external V
BUS
effective comparator.
0: Internal
1: External
22
DPSEL
R/W
DLine Pulsing Select
This bit selects the drive source of the data line pulse during SRP.
0
：
utmi_txvalid
1
：
utmi_termsel
23
SINI
R/W
Signal Invert
This bit indicates whether to invert ExternalVbusIndicator signal
0: Not invert
1: Invert; PHY inverts ExternalVbusIndicator input signal and
generates complementary output
24
NPTHQ
R/W
No Pass Through Qualified
This bit controls whether the complementary output verifies
through internal V
BUS
effective comparator
0: Pass
1: No pass
25
ULPIIPCDIS
R/W
ULPI Interface Protect Circuit Disable
0: Enable
1: Disable
28:26
Reserved
29
FHMODE
R/W
Forced Host Mode
0: Normal mode
1: Host mode, which takes effect 25ms later
30
FDMODE
R/W
Forced Device Mode
0: Normal mode
1: Device mode, which takes effect 25ms later
31
CTXP
R/W
Corrupt TX Packet
Debug bit, which cannot be set to 1.
