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Field
Name
R/W
Description
15:10
Reserved
19:16
TIMSEG1
R/W
Set the time segment 1 (Time Segment 1 Setup)
Time occupied by time period 1 tBS1 = tCAN x (1).
22:20
TIMSEG2
R/W
Set the time segment 2 (Time Segment 2 Setup)
Time occupied by time period 2 tBS2 = tCAN x (1).
23
Reserved
25:24
RSYNJW
R/W
Resynchronization Jump Width
Time that CAN hardware can extend or shorten in this bit tRJW=tCAN
x (1).
29:26
Reserved
30
LBKMEN
R/W
Loop Back Mode Enable
0: Disable
1: Enable
31
SILMEN
R/W
Silent Mode Enable
0: Normal state
1: Silent mode
Note: When CAN is in initialization mode, this register can be accessed only by software
CAN mailbox register
This section describes the transmitting and receiving mailbox registers.
The transmitting and receiving mailboxes are almost the same except the
following examples:
FMIDX domain of CAN_RXDLENx register;
The receiving mailbox is read-only;
The transmiting mailbox is writable only when it is empty, and if the
corresponding TXMEFLG bit of CAN_TXSTS register is 1, it means
the transmitting mailbox is empty.
There are three transmiting mailboxes and two receiving mailboxes in total.
Each receiving mailbox is FIFO with three levels of depth, and can only access
the message that is received first in FIFO.
Transmiting mailbox identifier register (CAN_TXMIDx) (x=0..2)
Offset address: 0x180, 0x190, 0x1A0
Reset value: 0xXXXX XXXX, X=undefined bit (except Bit 0, TXMREQ=0 after
reset)
Field
Name
R/W
Description
0
TXMREQ
R/W
Transmit Mailbox Data Request
0: When the data in the mailbox is sent, the mailbox is
empty and this bit is cleared by hardware
1: Software writes 1, to enable request to transmit
mailbox data
1
TXRFREQ
R/W
Transmit Remote Frame Request
0: Data frame
1: Remote frame
