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Structure block diagram
Figure 69 DCI Structure Block Diagram
Synchronizer
Data extraction
FIFO/Data
formatting
Control/State register
DMA interface
HCLK
HCLK
DCI_PIXCLK
DCI_D
DCI_HSYNC
DCI_VSYNC
Functional description
Signal description
The physical interface input signal of DCI (in slave mode) consists of
8/10/12/14-bit data DCI_ D, pixel clock PIXCLK, horizontal synchronization/data
valid HSYNC and vertical synchronization VSYNC. The signal description is
shown in the table below.
Table 83 DC signal Description
Name
Description
DCI_D
8/10/12/14-bit data captured by DCI,
PIXCLK
The data is synchronized with it and changes on the rising/falling edge of
PIXCLK according to the polarity
HSYNC
Indicate start or end of line
VSYNC
Indicate start or end of frame
Pixel clock cycle
The data captured by DCI can be 8 bits, 10 bits, 12 bits and 14 bits. To generate
a 32-bit data word, the number of pixel clock cycles needs to be different.
The 32-bit data word is divided into four 8-bit bytes, so DCI_D[7:0] can be
stored as 8-bit data, and DCI_D[9:0], DCI_D[11:0] and DCI_D[13:0] can be
stored as 10, 12 and 14 least significant bits of 16-bit words respectively, and
the remaining most significant bits will be cleared to 0. Therefore, 32-bit data
word can store four 8-bit data or two 10/12/14-bit data.
