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Field
Name
R/W
Description
21
STALLH
RW/RS
STALL Handshake
For uncontrolled and non-synchronous IN endpoints
(read/write mode is RW):
When this bit is set to 1, the device will reply STALL to all
tokens from the USB host. This bit can only be cleared to 0 by
software.
Used for control endpoints (read/write mode is RW)
When this bit is set to 1, it means that the module receives
SETUP token.
25:22
TXFNUM
R/W
TXFIFO Number
These bits indicate the FIFO number associated with the
endpoint, and a separate FIFO number needs to be set for each
effective IN endpoint.
26
NAKCLR
W
NAK Clear
When performing write operation to this bit, the NAK bit of the
endpoint will be cleared to 0.
27
NAKSET
W
NAK Set
When performing write operation to this bit, the NAK bit of the
endpoint will be set to 1.
This bit can control the transmission of NAK handshake signal.
28
DPIDSET
W
DATA0 PID Set
Used for interrupt/batch IN endpoints:
When performing write operation to this bit, PID will be set
to DATA0.
Even Frame Set
Used for synchronous IN endpoints:
When performing write operation to this bit, EOF will be set
to even frame.
29
OFSET
W
Odd Frame Set
It is used for synchronous OUT endpoints. When performing
write operation to this bit, EOF will be set to odd frame.
30
EPDIS
R/S
Endpoint Disable
Data transmission on the endpoint can be stopped by setting this
bit to 1.
This bit needs to be cleared to 0 before the endpoint disable
interrupt bit is set to 1; this bit can only be set to 1 after EPEN is
set to 1.
31
EPEN
R/S
Endpoint Enable
After this bit is set to 1, the endpoint will start to transmit data.
When any of the following interrupts is triggered, this bit will be
cleared to 0:
SETUP completed
Disable endpoint
Transmission completed
High-speed OTG device IN endpoint x interrupt register
(OTG_HS1_DIEPINTx) ( (x=0~7, endpoint number)
Offset address: 0x908+0x20m; m=0~7
