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the clock signal, the data unit manages the data transmission, and the
command unit manages the command transmission.
APB2 bus interface: Operate the registers in SDIO adapter, used for FIFO unit
for data transmission, generate an interrupt and DMA request signal.
Figure 114 SDIO Structure Block Diagram
SDIO
adapter
APB2
bus interface
SDIO
Interrupt
DMA
request
AHB bus
SDIO_CK
SDIO_CMD
SDIO_D[7:0]
SDIOCLK
HCLK/2
Register
FIFO
Control unit
Command unit
Data unit
Table 112 SDIO Pin Definition
Pin
Direction
Description
SDIO_CK
Output
MMC/SD/SD I/O card clock, clock line from master to card
SDIO_CMD
Bilateral
MMC/SD/SD I/O card command, bidirectional command signal
SDIO_D[7:0]
Bilateral
MMC/SD/SD I/O card data, bidirectional data bus
SDIO bus topology
After power-on reset, the master must initialize the device through a special
message-based bus protocol.
Each message is represented by one of the following parts:
Command: Command is a token to start an operation, from the
master to the card, and the command is transmitted to the CMD line
serially.
Response: From the card to the master, as a response to the
previously received command, the response is transmitted onto the
CMD serially.
