GR716-DS-UM, May 2019, Version 1.29
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GR716
10
PLL
10.1
Overview
The Phase-Lock-Loop (PLL) is capable of generating an phase locked output clock of 400MHz to the
system. The input reference clock is multiplied by 16, 20, 32, 40 or 80.
10.2
Operation
10.2.1 System overview
The PLL provides a 400MHz internal clock, typically used as SpaceWire clock, etc. The PLL refer-
ence-clock input is a 3.3V CMOS input, to which the XO-oscillator clock output can be directly con-
nected, or any other clock signal generated on PCB fulfilling the electrical specification of this input.
The PLL reference-clock input is allowed to be asynchronous to any other clocks in the GR716
LEON3FT microcontroller.
10.2.2 Detailed description
For more information about using the PLL in the system see section 4.
10.2.3 Access control
PLL status and configuration can be accessed via registers
10.2.4 Configuration protection
The PLL control registers are provided with an BCH EDAC that can correct and detect errors for the
PLL and clock configuration. When an correctable or uncorrectable error is detected an interrupt can
optionally be generated to the system.
In case of a uncorrectable error was detected the default configuration will be selected i.e. system
clock source is the external SYS_CLK pin
The protection scheme needs to be enabled by system to be active.
