GR716-DS-UM, May 2019, Version 1.29
291
www.cobham.com/gaisler
GR716
32
PacketWire Transmitter
32.1
Overview
The PacketWire Transmitter implements a transmit function with Direct Memory Access (DMA)
suppport. Packets (or blocks of data, normally CCSDS Space Packets) are automatically fetched from
memory, for which the user configures a descriptor table with descriptors that point to each individual
packet.
The core provides the following external and internal interfaces:
•
Packet Wire interface (serial bit data, bit clock, packet delimiter, abort, ready, busy)
•
AMBA AHB master interface, with sideband signals as per [GRLIB]
•
AMBA APB slave interface, with sideband signals as per [GRLIB]
The operation of the transmitter is highly programmable by means of control registers.
32.2
PacketWire interface
A PacketWire link comprises four ports for transmitting the message delimiter, the bit clock, the serial
bit data and an abort signal. A link also comprises additional ports for busy signalling, indicating
when the receiver is ready to receive the next octet, and for ready signalling, indicating that the
receiver is ready to receive a complete packet. The waveform format shown in figure 46.
Figure 46.
Synchronous bit serial waveform
The PacketWire protocol follows the CCSDS transmission convention, the most significant bit being
sent first, both for octet transfers (control), and for word transfer (address or data). Transmitted data
should consist of multiples of eight bits otherwise the last bits will be lost. The message delimiter port
Figure 45.
Block diagram
GRPWTX
DMA
AMBA
APB
Slave
PacketWire
FIFO
AMBA
AHB
Master
PacketWire output
AM
B
A
AH
B
A
M
BA
AP
B
CRC
Delimiter
Clock
Data
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
7
6
