GR716-DS-UM, May 2019, Version 1.29
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GR716
27
Clock gating unit (Secondary)
The GR716 microcontroller have 2 separate clock gating units. Each clock gating unit will control its
own clock domains and has a unique AMBA address described in chapter 2.11.
27.1
Overview
The clock gating unit provides a mean to save power by disabling the clock to unused functional
blocks. The core provides a mechanism to reset, enable clock and disable clock for following cores:
•
GRDMA
•
GR1553
•
GRCAN
•
GRSPW
•
GRADC
•
GRDAC
•
GRSEQ
The core provides a register interface via its APB slave bus interface.
27.2
Operation
The operation of the secondary clock gating unit is controlled through three registers: the unlock,
clock enable and core reset registers. The clock enable register defines if a clock is enabled or dis-
abled. A ‘1’ in a bit location will enable the corresponding clock, while a ‘0’ will disable the clock.
The core reset register allows to generate a reset signal for each generated clock. A reset will be gen-
erated as long as the corresponding bit is set to ‘1’. The bits in clock enable and core reset registers
can only be written when the corresponding bit in the unlock register is 1. If a bit in the unlock register
is 0, the corresponding bits in the clock enable and core reset registers cannot be written.
To gate the clock for a core, the following procedure should be applied:
1. Disable the core through software to make sure it does not initialize any AHB accesses
2. Write a 1 to the corresponding bit in the unlock register
3. Write a 0 to the corresponding bit in the clock enable register
4. Write a 0 to the corresponding bit in the unlock register
To enable the clock for a core, the following procedure should be applied
1. Write a 1 to the corresponding bit in the unlock register
2. Write a 1 to the corresponding bit in the core reset register
3. Write a 1 to the corresponding bit in the clock enable register
4. Write a 0 to the corresponding bit in the clock enable register
5. Write a 0 to the corresponding bit in the core reset register
6. Write a 1 to the corresponding bit in the clock enable register
7. Write a 0 to the corresponding bit in the unlock register