GR716-DS-UM, May 2019, Version 1.29
252
www.cobham.com/gaisler
GR716
respectively one descriptor for M2B transfers and one for B2M transfers. Conditional descriptors are
not supported in this mode. The descriptors are written directly onto GRDMAC via APB at offsets
0x20 and 0x30. Their next_descriptor field is hardwired to zeroes. Their status is always written-back
to their relative descriptor status register.
When the core is configured in Simplified mode of operation, the relative bit (SM) must be set to one
in the control register. The core will execute the two internal descriptors on channel zero. Channel
zero must therefore be enabled, and the core status can be read on channel zero’s status bits in the sta-
tus register.
28.4
AHB transfers
For every descriptor executed, GRDMAC will perform an AHB data transfer at the address and of the
size specified. The AHB accesses can be at aligned or unaligned memory addresses.
The core will perform unaligned memory access if defined by the descriptors. It will perform byte (8
bit) accesses at byte-aligned addresses, half-word (16 bit) accesses at half-word aligned addresses
In some cases, the total transfer size might require GRDMAC to perform additional half-word and/or
byte accesses at the end of the transfer. The burst accesses performed by GRDMAC are of type incre-
menting burst of unspecified length. These bursts will never cross a 1KB memory boundary. At the
1KB memory boundary the burst will be interrupted, an idle cycle will be inserted and the increment-
ing burst of unspecified length will restart from the next address.
28.5
Interrupts
GRDMAC provides fine-grained control of interrupt generation. At the highest level, the global Inter-
rupt Enable bit (IE) in the control register can be set to zero to mask every other interrupt setting in the
system. If set to one, interrupt generation depends on the following settings.
The Interrupt on Error Enable bit (IEE) in the control register provides a way to generate interrupts in
the event of errors. Error generation is discussed further in the next paragraph.
An interrupt can be also generated by the successful completion of a descriptor, if the Interrupt Enable
(IE) bit is set to one in the descriptor’s control field. The Interrupt Mask bit (Ix) in the Interrupt Mask
register can be set to zero to mask all the descriptor completion interrupts. If descriptor write-back is
enabled, the interrupt will be generated after writing back the descriptor’s status in main memory.
For both interrupts on error and interrupts on descriptor completion events, a flag will be raised in the
interrupt flag register at the bit corresponding to the channel where the interrupt event happened (IFx).
As an example of interrupt generation setup, one can enable interrupt on channel completion by per-
forming the following steps. The Interrupt Enable (IE) bit in GRDMAC control register must be set to
one, as must be the relevant channel’s interrupt mask bit in the Interrupt mask register. Finally the
Interrupt Enable (IE) bit in the control field of the last descriptor in the B2M chain of the channel
must be set to one, while the same field must be set to zero in every other descriptor in the channel.
This way, when the last descriptor in the buffer to memory chain is completed successfully, an inter-
rupt will be generated.
28.6
Errors
Six types of errors can be generated by GRDMAC. Transfer errors, descriptor errors, Channel Vector
Pointer errors, conditional errors, conditional type 1 retry error, conditional type 1 counter error and
timeout errors, as defined in the Error Register.
Transfer errors are generated when the core is accessing DMA data from and to memory and it
encounters an AMBA AHB ERROR response. When a transfer error occurs on a descriptor which has
the write-back flag enabled, the descriptor status will be written back to main memory with the error
field set to one. An eventual interrupt will be generated only after the write back.