GR716-DS-UM, May 2019, Version 1.29
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16.2.11 Single vector trapping (SVT)
Single-vector trapping (SVT) is an SPARC V8e option to reduce code size for embedded applications.
When enabled, any taken trap will always jump to the reset trap handler (%tbr.tba + 0). The trap type
will be indicated in %tbr.tt, and must be decoded by the shared trap handler. SVT is enabled by setting
bit 13 in %asr17.
16.2.12 Address space identifiers (ASI)
In addition to the address, a SPARC processor also generates an 8-bit address space identifier (ASI),
providing up to 256 separate, 32-bit address spaces. During normal operation, the LEON3 processor
accesses instructions and data using ASI 0x8 - 0xB as defined in the SPARC manual. Using the LDA/
STA instructions, alternative address spaces can be accessed. The different available ASIs are
described in section 16.6.
16.2.13 Partial WRPSR
The processor has support for partial WRPSR. Partial write %PSR (WRPSR) is a SPARC V8e option
that allows WRPSR instructions to only affect the %PSR.ET field.
16.2.14 Alternative window pointer
Alternative window pointer (AWP) is a SPARC V8e option intended to reduce interrupt latency by
allowing code that manipulates the current window pointer, mainly window over and underflow han-
dlers and context switching code, to run with traps enabled.
Two bits are added to the PSR register, AW (alternative window) and PAW (previous alternative win-
dow). Also an AWP (alternative window pointer) field is added in an ASR register.
When the AW bit is set, the current register window used for reading/writing non-global registers is
taken from the AWP register field instead of the normal CWP register field, and SAVE and
RESTORE operations modify the AWP field instead of the CWP. SAVE and RESTORE can do not
trigger the window over/underflow traps while AW is set.
When both AW and PAW are zero, the AWP field is kept equal to the CWP field.
When a trap occurs, the value of AW is copied into the PAW field, and AW is cleared. When returning
from a trap using the RETT instruction, the PAW field is copied back into AW. The RETT will not
trigger the window underflow trap if PAW is set regardless of if CWP or AWP point to an invalid win-
dow.
16.2.15 Register file partitioning
Register file partitioning is an optional extension to allow a subrange of the register windows to be
used as if it was the whole register file. The selected subset is connected in a ring so that the outs of
the lowest register window is aliased to the ins of the highest register window in the range. Other reg-
ister windows outside this range are not accessible and will be kept at their old values while the parti-
tioning is enabled.
The partitioning is activated by setting the STWIN and CWPMAX fields of the %asr20 register. This
selects the subset of windows between STWIN and STWIN+CWPMAX so that they map to CWP
values 0 to CWPMAX. STWIN and CWPMAX must be set so they map to a valid range, CWP-
MAX+STWIN must not exceed the highest possible CWP value supported in the normal case. Also,
for correct operation, CWP must be set to a value between 0 and CWPMAX before accessing any
non-global register.
Writing CWPMAX to (otherwise illegal value) 0 in %asr20 will result in writing only AWP and keep-
ing the values of STWIN and CWPMAX.