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If the data bit rate is too high for a slave device or if the slave needs time to process data, it may
stretch the clock period by keeping SCL low after the master has driven SCL low. Clock stretching is
a configurable parameter of the core (see sections 37.2.4 and 37.2.6).
37.2.2 Slave addressing
The core responds to two addresses on the I
2
C bus. Accesses to the I2C memory address are translated
to AMBA AHB accesses and accesses to the I
2
C configuration address access the core’s configuration
register. I2C memory and slave addresses can be configured via control registers see register
SLVADDR
and SLVCFG in section 37.3.5 and 37.3.6.
37.2.3 System clock requirements and sampling
The core samples the incoming I
2
C SCL clock and does not introduce any additional clock domains
into the system. Both the SCL and SDA lines first pass through two stage synchronizers and are then
filtered with a low pass filter consisting of four registers.
START and STOP conditions are detected if the SDA line, while SCL is high, is at one value for two
system clock cycles, toggles and keeps the new level for two system clock cycles.
The synchronizers and filters constrain the minimum system frequency. The core requires the SCL
signal to be stable for at least four system clock cycles before the core accepts the SCL value as the
new clock value. The core’s reaction to transitions will be additionally delayed since both lines are
taken through two-stage synchronizers before they are filtered. Therefore it takes the core over eight
system clock cycles to discover a transition on SCL.
37.2.4 Configuration register access
The I
2
C configuration register is accessed via a separate I
2
C address (I
2
C configuration address). The
configuration register has the layout shown in table 505.
Table 505.
I2C2AHB configuration register
7
6
5
4
3
2
1
0
Reserved
PROT
MEXC
DMAACT
NACK
HSIZE
7:6
Reserved, always zero (read only)
5
Memory protection triggered (PROT) - ‘1’ if last AHB access was outside the allowed
memory area. Updated after each AMBA access (read only)
4
Memory exception (MEXC) - ‘1’ if core receives AMBA ERROR response. Updated
after each AMBA access (read only)
3
DMA active (DMAACT) - ‘1’ if core is currently performing a DMA operation.
Figure 58.
Complete I
2
C data transfer
START MSB
LSB
R/W ACK
SCL
SDA
continued...
Slave address
1 2 3 4 5 6 7 8 9
MSB
LSB ACK STOP
SCL
SDA
Data
1 2 3 4 5 6 7 8 9
