GR716-DS-UM, May 2019, Version 1.29
461
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GR716
46.1
Overview
The core maps a memory device connected via the Serial Peripheral Interface (SPI) into AMBA
address space. Read accesses are performed by performing normal AMBA read operations in the
mapped memory area. Other operations, such as writes, are performed by directly sending SPI com-
mands to the memory device via the core’s register interface. The core is highly configurable and sup-
ports most SPI Flash memory devices.
46.2
Operation
46.2.1 Operational model
The core has two memory areas that can be accessed via the AMBA bus; the I/O area and the ROM
area. The ROM area maps the memory device into AMBA address space and the I/O area is utilized
for status reporting and to issue user commands to the memory device.
When transmitting SPI commands directly to the device the ROM area should be left untouched. The
core will issue an AMBA ERROR response if the ROM area is accessed when the core is busy per-
forming an operation initiated via I/O registers.
Depending on the type of device attached the core may need to perform an initialization sequence.
Accesses to the ROM area during the initialization sequence receive AMBA error responses. The core
has successfully performed all necessary initialization when the Initialized bit in the core’s status reg-
ister is set.
46.2.2 I/O area
The I/O area contains registers that are used when issuing commands directly to the memory device.
By default, the core operates in System mode where it will perform read operations on the memory
device when the core’s ROM area is accessed. Before attempting to issue commands directly to the
memory device, the core must be put into User mode. This is done by setting the User Control
(USRC) bit in the core’s Control register. Care should be taken to not enter User mode while the core
is busy, as indicated by the bits in the Status register. The core should also have performed a success-
ful initialization sequence before User mode accesses (INIT bit in the Status register should be set).
Note that a memory device may need to be clocked when there has been a change in the state of the
chip select signal. It is recommended that software transmits a byte with the memory device dese-
lected after entering and before leaving User mode.
The following steps are performed to issue a command to the memory device after the core has been
put into User mode:
1. Check Status register and verify that the BUSY and DONE bits are cleared. Also verify that the
core is initialized and not in error mode.
2. Optionally enable DONE interrupt by setting the Control register bit IEN.
3. Write command to Transmit register.
Figure 79.
Block diagram
A
M
B
A
A
H
B
AHB control
Register interface
Control FSM
SCK
CSN
Flash control FSM
SPI
MISO
MOSI
ERRORN
READY
INITIALIZED