GR716-DS-UM, May 2019, Version 1.29
126
www.cobham.com/gaisler
GR716
A special write-only bit in the %asr20 register can be used to write CWP in the PSR at the same time
as writing the STWIN,CWPMAX,AWP fields, this is intended to allow switching between two regis-
ter file partitions without disabling interrupts.
The WIM register is not managed by the partitioning logic, therefore the lowest bits of the WIM will
map to the partitioned windows. The highest bits of the WIM will be masked to 0 on read to simulate
a smaller register file, however these bits are still writable.
16.2.16 Power-down
The processor can enter a power-down mode to minimize power consumption during idle periods.
The power-down mode is entered by performing a WRASR instruction to %asr19:
wr %g0, %asr19
During power-down, the pipeline is halted until the next interrupt occurs. Signals inside the processor
pipeline are then static, reducing power consumption from dynamic switching.
Note: %asr19 must always be written with the data value zero to ensure compatibility with future
extensions.
Note: This instruction must be performed in supervisor mode with interrupts enabled.
When resuming from power-down, the pipeline will be re-filled from the point of power-down and the
first instruction following the WRASR instruction will be executed prior to taking the interrupt trap.
Up to six instructions after the WRASR instruction will be fetched prior to fetching the trap handler.
16.2.17 Processor reset operation
The processor is reset by asserting the RESET input for at least 4 clock cycles. The following table
indicates the reset values of a subset of the registers which are affected by the reset..
By default, the execution will start from address 0 and is taken from the register processor boot
address register in the interrupt controller. This allows processor to be dynamically restarted and the
reset address to be changed dynamically and can e.g. when new software has been remotely uploaded
and processor should restart.
16.2.18 LEON-REX extension
The processor supports the LEON-REX addition to the SPARC instruction set, allowing a more com-
pact code representation than the regular SPARC machine code, see reference document [LEON-
REX]
Detection whether support is present can be done by checking the REXV field in the asr17 register
(see section 16.6.2). The REX support can be set to enabled, illegal or transparent mode via the
REXEN/REXILL bits in the asr17 register, after reset the default setting is illegal so any LEON-REX
code will cause an illegal instruction trap.
16.2.19 Constant interrupt delay
The LEON3FT is enhanced with an interrupt zero jitter feature. When the interrupt zero jitter feature
is enabled all sources of interrupt jitter introduced by the hardware can be eliminated. The latency is
Table 116.
Processor reset values
Register
Reset value
Trap Base Register
Trap Base Address field reset (value 0)
PC (program counter)
0x0
nPC (next program counter)
0x4
PSR (processor status register)
ET=0, S=1
