GR716-DS-UM, May 2019, Version 1.29
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GR716
An I
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C slave may also support 10-bit addressing. In this case the master first transmits a pattern of
five reserved bits followed by the two first bits of the 10-bit address and the R/W bit set to ‘0’. The
next byte contains the remaining bits of the 10-bit address. If the transfer is a write operation the mas-
ter then transmits data to the slave. To perform a read operation the master generates a repeated
START condition and repeats the first part of the 10-bit address phase with the R/W bit set to ‘1’.
If the data bitrate is too high for a slave device or if the slave needs time to process data, it may stretch
the clock period by keeping SCL low after the master has driven SCL low.
39.2.2 Slave addressing
The core have a programmable address and support for 7-bit and 10-bit addresses. The core is config-
ured to use 10-bit address as default. The address mode controlled with the TBA bit in the Slave
address register.
39.2.3 System clock requirements and sampling
The core samples the incoming I
2
C SCL clock and does not introduce any additional clock domains
into the system. Both the SCL and SDA lines first pass through two stage synchronizers and are then
filtered with a low pass filter consisting of four registers.
START and STOP conditions are detected if the SDA line, while SCL is high, is at one value for two
system clock cycles, toggles and keeps the new level for two system clock cycles.
The synchronizers and filters constrain the minimum system frequency. The core requires the SCL
signal to be stable for at least four system clock cycles before the core accepts the SCL value as the
new clock value. The core’s reaction to transitions will be additionally delayed since both lines are
taken through two-stage synchronizers before they are filtered. Therefore it takes the core over eight
system clock cycles to discover a transition on SCL. To use the slave in Standard-mode operation at
100 kHz the recommended minimum system frequency is 2 MHz. For Fast-mode operation at 400
kHz the recommended minimum system frequency is 6 MHz.
39.2.4 Operational model
The core has four main modes of operation and is configured to use one of these modes via the Con-
trol register bits Receive Mode (RMOD) and Transmit Mode (TMOD). The mode setting controls the
core’s behavior after a byte has been received or transmitted.
The core will always NAK a received byte if the receive register is full when the whole byte is
received. If the receive register is free the value of RMOD determines if the core should continue to
listen to the bus for the master’s next action or if the core should drive SCL low to force the master
Figure 64.
Complete I
2
C data transfer
START MSB
LSB
R/W ACK
SCL
SDA
continued...
Slave address
1 2 3 4 5 6 7 8 9
MSB
LSB ACK STOP
SCL
SDA
Data
1 2 3 4 5 6 7 8 9
