GR716-DS-UM, May 2019, Version 1.29
233
www.cobham.com/gaisler
GR716
4. Write a 0 to the corresponding bit in the clock enable register
5. Write a 0 to the corresponding bit in the core reset register
6. Write a 1 to the corresponding bit in the clock enable register
7. Write a 0 to the corresponding bit in the unlock register
The clock gating unit also provides gating for the processor core and floating-point unit. The proces-
sor core will be automatically gated off when it enters power-down mode.
The FPU will be gated off when the LEON3FT processor core connected to the FPU have floating-
point disabled or when the LEON3FT processor core is in power-down mode.
Processor/FPU clock gating can be disabled by writing ‘1’ to bit 0 of the CPU/FPU override register.
26.3
Registers
The core’s registers are mapped into APB address space.
Table 256.
Clock gate unit registers
APB address offset
Register
0x00
Unlock register 0
0x04
Clock enable register 0
0x08
Core reset register 0
0x0C
CPU/FPU override register 0
0x10 - 0xFF
Reserved
