GR716-DS-UM, May 2019, Version 1.29
330
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GR716
33.11.7 DMA Control/Status
Table 407.
0x20 - DMACTRL - DMA control/status
31
26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
INTNUM
RES
EP TR IE IT RP TP TL LE SP SA EN NS RD RX AT RA TA PR PS AI RI TI RE TE
*
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
rw
r
wc wc rw rw wc wc wc rw rw rw rw rw rw
r
rw wc wc wc wc rw rw rw rw rw
31: 26
Interrupt-number (INTNUM) - The interrupt-number used for this DMA channel when sending an
interrupt-code that was generated due to any of the events maskable by the DMACTRL.IE and
DMACTRL.IT bits. Reset value is taken from the IRQTXDEFAULT input signal. Field is only pres-
ent if interrupt distribution is supported, which is indicated by the CTRL.ID bit. Note that this field
must be set to a value within the range defined by the INCTRL.NUMINT and INTCTRL.BASEINT
fields. A value outside the range will result in no interrupt-code being sent.
25: 24
RESERVED
23
EEP termination (EP) - Set to 1 when a received packet for the corresponding DMA channel ended
with an Error End of Packet (EEP) character.
22
Truncated (TR) - Set to 1 when a received packet for the corresponding DMA channel is truncated
due to a maximum length violation.
21
Interrupt-code transmit enable on EEP (IE) - When set to 1, and the interrupt-code transmit enable
bit (INTCTRL.IT) is set, an interrupt-code is generated when a received packet on this DMA chan-
nel ended with an Error End of Packet (EEP) character. Field is only present if interrupt distribution
is supported, which is indicated by the CTRL.ID bit.
20
Interrupt-code transmit enable on truncation (IT) - When set to 1, and the interrupt-code transmit
enable (INTCTRL.IT) bit in the Interrupt distribution control register is set, an interrupt-code is gen-
erated when a received packet on this DMA channel is truncated due to a maximum length violation.
Field is only present if interrupt distribution is supported, which is indicated by the CTRL.ID bit.
19
Receive packet IRQ (RP) - This bit is set to 1 when an AMBA interrupt was generated due to the fact
that a packet was received for the corresponding DMA channel.
18
Transmit packet IRQ (TP) - This bit is set to 1 when an AMBA interrupt was generated due to the
fact that a packet was transmitted for the corresponding DMA channel.
17
Transmitter enable lock (TL) - This bit is set to 1 if the CTRL.TL bit is set, and the transmitter for the
corresponding DMA channel is disabled due to a link error (controlled by the DMACTRL.LE bit).
While this bit is set, it is not possible to re-enable the transmitter (e.g. not possible to set the DMAC-
TRL.TE bit to 1).
16
Link error disable (LE) - Disable transmitter when a link error occurs. No more packets will be trans-
mitted until the transmitter is enabled again.
15
Strip pid (SP) - Remove the pid byte (second byte) of each packet. The address byte (first byte) will
also be removed when this bit is set, independent of the value of the DMACTRL.SA bit.
14
Strip addr (SA) - Remove the addr byte (first byte) of each packet.
13
Enable addr (EN) - Enable separate node address for this channel.
12
No spill (NS) - If cleared, packets will be discarded when a packet is arriving and there are no active
descriptors. If set, the core will wait for a descriptor to be activated.
11
Rx descriptors available (RD) - Set to one, to indicate to the core that there are enabled descriptors in
the descriptor table. Cleared by the core when it encounters a disabled descriptor.
10
RX active (RX) - Is set to ‘1’ if a reception to the DMA channel is currently active, otherwise it is
‘0’.
9
Abort TX (AT) - Set to one to abort the currently transmitting packet and disable transmissions. If no
packet is currently being transmitted, the only effect is to disable transmissions. Self clearing.
