GR716-DS-UM, May 2019, Version 1.29
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GR716
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Configuration register will set and cleared using a double store from the processor written from
the processor.
The actual bit field operation is performed in the APB bridge and in the local on-chip data RAM and
will have no impact on the instruction execution or delay of data fetch. Atomic accesses are further
described in section 2.12.
2.2.7
Remote access and control
The microcontroller can be accessed and controlled by an external control unit via SpaceWire
(RMAP), UART, SPI or I2C without using processor support. Full access, except for debug features
on the debug AMBA bus, will be granted to SpaceWire, UART, SPI or I2C if enabled at startup via
bootstraps after reset:
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SpaceWire: Remote Memory Access Protocol (RMAP) provides full remote access to the entire
AMBA address space of the microcontroller. See section for GRSPW2 for more information
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UART: Support for reading and writing to register via special protocol over UART provides full
remote access to the entire AMBA address space of the microcontroller. See section for
AHBUART for more information
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SPI: Support for reading and writing to register via special protocol over SPI provides full
remote access to the entire AMBA address space of the microcontroller. See section for
SPI2AHB for more information
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I2C: Support for reading and writing to register via special protocol over I2C provides full
remote access to the entire AMBA address space of the microcontroller. See section for
I2C2AHB for more information
All the communication interfaces above can be implemented to be functional directly after the micro-
controller leaves reset, no initialisation from the processor is required. The communication links can
also be disabled by the processor, a feature that can be required for safety.
When debugging the microcontroller, the DSU is used to load software and initiate the program
counter. In the case when new software is remotely updated via SpaceWire, UART, SPI or I2C, a spe-
cial feature in the interrupt handler is implemented to restart the system and to start execution of new
software. For more information see section 40.2.7 to 40.2.9.
2.2.8
Pin sharing
A I/O switch matrix allows most of the GR716 microcontroller pins functionality to be configurable
and to be shared between several peripherals. The I/O switch matrix provides a flexible solution
where enabling one core changes the I/O switch matrix so that the current core gets connected to I/O
pads.
The microcontroller comprises on-chip ADC/DAC. The on-chip ADC/DAC requires special mixed
digital and analog I/Os. The mixed digital and analog I/O is controlled via configuration registers and
needs to be set to analog mode when an ADC or DAC is going to be used.
SPI4SPACE supports on-chip LVDS transceivers and CMOS I/Os. The redundant SPI4SPACE chan-
nel can be accessed via CMOS pins and the primary SPI4SPACE channel is accessed via on-chip
LVDS.
2.2.9
Integrated ADC and DAC
The ADC digital control logic supports functions to control the on-chip ADC and to offload the pro-
cessor. Support for automatic oversampling on all channels, sample sequencer and digital level com-
parators are examples of features integrated to offload the processor. The integrated DMA controller
can also be used to off-load the processor by automatic transfers of sample values to/from the inte-
grated data and ADC/DAC.
