GR716-DS-UM, May 2019, Version 1.29
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GR716
To set up a triggering conditional descriptor, the
I
T bit field in the descriptor’s control field needs to
be set to ‘1’. Bits 5:0 of the conditional address/triggering line field will specify which of the 64 input
lines of the IRQ_TRIG signal will be monitored. During the execution of the triggering conditional
descriptor, the triggering line is monitored every clock cycle, and when the value of the line is ‘1’, the
conditional execution will terminate and the data descriptor will be yield, fetching COND_SIZE bytes
before going back to executing the conditional triggering. The data descriptor will be considered com-
pleted when all the bytes from the data descriptor, specified in the SIZE field, have been transfered, in
amounts of COND_SIZE at each triggering. An optional timeout counter can be enabled during the
triggering conditional descriptor execution. By setting the TE bit field in the core’s control register to
‘1’ and by setting the Timer Reset Value Register to the required number of clock cycles, the descrip-
tor execution is halted with a Timeout Error if an interrupt is not received before the timer expires.
The error halts the channel execution after eventual descriptor write-back is performed.
To set up a polling conditional descriptor, the DT bit field in the descriptor’s control field needs to be
set to ‘0’. Bits 31:0 of the conditional address/triggering line field will point to the address that the
DMA core will poll for data until the termination condition is TRUE. The condition is specified as the
bitwise AND between the 32-bit word pointed by COND_ADDR and the COND_MASK. This value
is compared to 0 according to the following formulas, according to the termination condition type
selected in the conditional control field (CT).
When the condition is TRUE, the conditional descriptor will stop polling and will proceed with fetch-
ing COND_SIZE bytes from the data descriptor pointed by NEXT_PTR. The behavior of conditional
descriptors is explained in depth in paragraph 28.3.2.
Also in paragraph 28.3.2 is an example configuration of a conditional DMA channel for UART read-
ing.
Fields that are named RESERVED, RES, or R are read-only fields. These fields can be writ-
ten with zero or with the value read from the same register field.
Table 276.
GRDMAC Conditional descriptor Termination condition type 0
Table 277.
GRDMAC Conditional descriptor Termination condition type 1
Table 278.
GRDMAC Conditional descriptor format
Address offset
Field
0x0
Conditional next_descriptor
0x4
Conditional address/triggering line
0x8
Conditional control
0xC
Conditional mask
Table 279.
GRDMAC Conditional descriptor next_descriptor field (address offset 0x00)
31
4
3
1
0
NEXT_PTR
VER
DT
*COND_ADDR COND_MASK
0
=
*COND_ADDR COND_MASK
0
