GR716-DS-UM, May 2019, Version 1.29
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GR716
28.2.8 Register setup
Once the channel vector and the relative descriptor chain are setup in main memory, the GRDMAC
register must be also setup. The 128-byte-aligned address, where the Channel Vector resides, must be
written in the Channel Vector Pointer register. The control register must also be setup. Once the
enable bit of the control register is set to one, the core will start running and will execute all the chan-
nels which are enabled.
28.3
Operation
28.3.1 Normal mode of operation
In normal mode of execution, GRDMAC will start executing all the enabled channels until they are
complete or an error is generated.
When executing a DMA channel, the core will initially fetch the two descriptor pointers from the
address provided in the CVP register which are relative to the channel. It will then fetch the first M2B
and B2M descriptors from main memory. The M2B descriptor chain is then executed until either the
internal buffer is full, or the M2B chain is completed. If one of this events happen, the core will switch
to the B2M descriptor chain. The B2M chain will switch back to the M2B chain when the buffer is
empty. The DMA channel is marked complete when the last descriptor in the B2M chain is executed,
finally emptying the buffer.
During the execution of a chain, the core will fetch a new descriptor after the successful completion of
the previous one, following the pointers in the linked list. When the core reaches a NULL pointer in
the M2B chain, it will switch to the B2M chain. When it reaches a NULL pointer in the B2M chain,
the core will update the DMA channel status and switch to the next enabled DMA channel, until all
the channels are completed.
28.3.2 Operation with conditional descriptors
Conditional descriptors bond to the following data descriptor in the linked list and provide conditional
behavior to the execution of the data descriptor. During the execution of a DMA channel, when the
core fetches a conditional descriptor from memory, it will proceed and fetch the following descriptor
in the chain as well, which must be a data descriptor.
After the descriptors’ pair has been fetched, the conditional execution will follow these steps:
a
) the core will execute the conditional counter, down counting for COUNTER_RST clock cycles
b
) if the conditional descriptor is a polling descriptor, go to step
c1
, if it’s a triggering descriptor, go
to step
c2
.
c1
) the core will fetch a 32-bit word at the COND_ADDR address.
Table 293.
GRDMAC Conditional descriptor protection field for version 1 (address offset 0x1C)
31
30
0
PE
COND_CRC
31
Conditional Protection Enable (PE) - Enable descriptor validation check of descriptor. If ’1’ an extra
check will be performed to make sure the descriptors are read correctly into the memory
30
: 0
Conditional descriptor data CRC (COND_CRC) - Data checksum for conditional type 1 descriptors