COBHAM GR716, Advanced Data Sheet And User’S Manual, Page: 155 / 547

GR716-DS-UM, May 2019, Version 1.29 157 www.cobham.com/gaisler
GR716
19.7.12 Instruction trace control register 0
The instruction trace control register 0 contains a pointer that indicates the next line of the instruction
trace buffer to be written.
19.7.13 Instruction trace control register 1
The instruction trace control register 1 contains settings used for trace buffer overflow detection. This
register can be written while the processor is running.
NR 0
rw r
31: 2 Break point address (BADDR) - Bits 31:2 of breakpoint address
1: 0 Read as 0b00
Table 152.
0x000054, 0x00005C - ATBBM - AHB trace buffer break mask register
31 2 1 0
BMASK[31:2] LD ST
NR 0 0
rw rw rw
31: 2 Breakpoint mask (BMASK) - (see text)
1 Load (LD) - Break on data load address
0 Store (ST) - Break on data store address
Table 153.
0x110000 - ITBCO - Instruction trace control register 0
31 29 28 16 15 0
RESERVED ITPOINTER
0 NR
r rw
31: 28 Trace filter configuration
27: 16 RESERVED
15: 0 Instruction trace pointer (ITPOINTER)
Table 154.
0x110004 - ITBCI - Instruction trace control register 1
31 28 27 26 24 23 22 0
RESERVED W
O
TLIM OV RESERVED
0 0 0 0 0
r rw rw rw r
31: 28 RESERVED
27 Watchpoint on overflow (WO) - If this bit is set, and Break on iu watchpoint (BW) is enabled in the
DSU control register, then a watchpoint will be inserted when a trace overflow is detected (TOV
field in this register gets set).
26: 24 Trace Limit (TLIM) - TLIM is compared with the top bits of ITPOINTER in Instruction trace con-
trol register 0 to generate the value in the TOV field below.
23 Trace Overflow (TOV) - Gets set to ‘1’ when the DSU detects that TLIM equals the top three bits of
ITPOINTER.
22: 0 RESERVED
Table 151.
0x000050, 0x000058 - ATBBA - AHB trace buffer break address register