GR716-DS-UM, May 2019, Version 1.29
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GR716
scaler value = (system_clock_frequency) / (baud_rate * 8) - 1
18.4
Loop back mode
If the LB bit in the UART control register is set, the UART will be in loop back mode. In this mode,
the transmitter output is internally connected to the receiver input and the RTSN is connected to the
CTSN. It is then possible to perform loop back tests to verify operation of receiver, transmitter and
associated software routines. In this mode, the outputs remain in the inactive state, in order to avoid
sending out data.
18.5
FIFO debug mode
FIFO debug mode is entered by setting the debug mode bit in the control register. In this mode it is
possible to read the transmitter FIFO and write the receiver FIFO through the FIFO debug register.
The transmitter output is held inactive when in debug mode. A write to the receiver FIFO generates an
interrupt if receiver interrupts are enabled.
18.6
Interrupt generation
Two different kinds of interrupts are available: normal interrupts and FIFO interrupts.
Normal interrupts from the transmitter are generated when transmitter interrupts are enabled (TI), the
transmitter is enabled and the transmitter FIFO goes from containing data to being empty. For the
receiver normal interrupts are generated when receiver interrupts are enabled (RI), the receiver is
enabled and a character is received. The interrupt is generated if the character is correct and stored in
the receive FIFO or if an error, such as parity; framing or overrun occurred.
Transmitter FIFO interrupts are generated when the transmitter FIFO interrupts are enabled (TF),
transmissions are enabled (TE) and the UART is less than half-full (that is, whenever the TH status bit
is set). This is a level interrupt and the interrupt signal is continuously driven high as long as the con-
dition prevails. Receiver FIFO interrupts are generated when receiver FIFO interrupts are enabled
(RF), the receiver is enabled and the FIFO is half-full. The interrupt signal is continuously driven high
as long as the receiver FIFO is half-full (at least half of the entries contain data frames).
Note that the processor acknowledges and clears the corresponding interrupt pending register but for
FIFO interrupts the interrupt signal from the UART is continuously driven high, resulting in a new
pending interrupt immediately being set in the interrupt controller. If FIFO interrupts are used for con-
trolling FIFO handling, an interrupt handler need to check that there is room in the transmit FIFO
before writing and that characters are available in the receive FIFO before reading.
To reduce interrupt occurrence a delayed receiver interrupt is available. It is enabled using the delayed
interrupt enable (DI) bit. When enabled a timer is started each time a character is received and an
interrupt is only generated if another character has not been received within 4 cha 4 bit times.
If receiver FIFO interrupts are enabled a pending character interrupt will be cleared when the FIFO
interrupt is active since the character causing the pending irq state is already in the FIFO and is
noticed by the driver through the FIFO interrupt. In order to not take one additional interrupt, software
should clear the corresponding pending bit after the FIFO has been emptied.
There is also a separate interrupt for break characters. When enabled an interrupt will always be gen-
erated immediately when a break character is received even when delayed receiver interrupts are
enabled. When break interrupts are disabled no interrupt will be generated for break characters when
delayed interrupts are enabled.
When delayed interrupts are disabled the behavior is the same for the break interrupt bit except that an
interrupt will be generated for break characters if receiver interrupt enable is set even if break inter-
rupt is disabled.
An interrupt can also be enabled for the transmitter shift register. When enabled the core will generate
an interrupt each time the shift register goes from a non-empty to an empty state.
