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COBHAM GR716, Advanced Data Sheet And User’S Manual

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COBHAM GR716 Advanced Data Sheet And User’S Manual Download Page 432

GR716-DS-UM, May 2019, Version 1.29

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www.cobham.com/gaisler

GR716

ordering, clock gap insertion, automatic slave select and automatic periodic transfers of a specified 
length. All SPI modes are supported and also a 3-wire mode where one bidirectional data line is used. 
In slave mode the core synchronizes the incoming clock and can operate in systems where other SPI 
devices are driven by asynchronous clocks.

44.2

Operation

44.2.1 SPI transmission protocol

The SPI bus is a full-duplex synchronous serial bus. Transmission starts when a master selects a slave 
through the slave’s Slave  Select (SLVSEL) signal and  the clock line  SCK transitions  from  its idle 
state. Data is transferred from the master through the Master-Output-Slave-Input (MOSI) signal and 
from the slave through the Master-Input-Slave-Output (MISO) signal. In a system with only one mas-
ter and one slave, the Slave Select input of the slave may be always active and the master does not 
need to have a slave select output. If the core is configured as a master it will monitor the SPISEL sig-
nal to detect collisions with other masters, if SPISEL is activated the master will be disabled.
During a transmission on the SPI bus data is either changed or read at a transition of SCK. If data has 
been read at edge n, data is changed at edge n+1. If data is read at the first transition of SCK the bus is 
said to have clock phase 0, and if data is changed at the first transition of SCK the bus has clock phase 
1. The idle state of SCK may be either high or low. If the idle state of SCK is low, the bus has clock 
polarity 0 and if the idle state is high the clock polarity is 1. The combined values of clock polarity 
(CPOL)  and  clock  phase  (CPHA)  determine  the  mode  of  the  SPI  bus.  Figure  74  shows  one  byte 
(0x55) being transferred MSb first over the SPI bus under the four different modes. Note that the idle 
state of the MOSI line is ‘1’ and that CPHA = 0 means that the devices must have data ready before 
the first transition of SCK. The figure does not include the MISO signal, the behavior of this line is 
the same as for the MOSI signal. However, due to synchronization issues the MISO signal will be 
delayed when the core is operating in slave mode, please see section 44.2.5 for details.

Figure 73.  

Block diagram

A

M

B

A

A

P

B

Transmit

MISO

Mode register

Event register

Mask register

Com. register

Transmit register

Receive register

Slave select reg.

FIFO

Receive

FIFO

SCK

Control

Master ctrl

Slave ctrl

Clock gen.

S

y

n

c

r

e

g

i

s

t

e

r

s

SPISEL

SLVSEL

MOSI

SPICTRL

Summary of Contents for GR716

Page 1: ...c package Total Ionizing Dose TID up to 100 krad Si Single Event Latch up Immunity SEL to LETTH 118 MeV cm2mg Single Event Upset SEU below 10 6 errors per device and day in space environment TBC Suppo...

Page 2: ...I O switch matrix pin validation script 39 2 9 I O switch matrix scenario examples 42 2 10 Cores 48 2 11 Memory map 49 2 12 Interrupts 54 3 Signals 56 3 1 Bootstrap signals 56 3 2 Configuration for f...

Page 3: ...sters 107 13 LDO 112 13 1 Overview 112 13 2 Operation 112 14 Temperature Sensor 113 14 1 Overview 113 14 2 Operation 113 15 DAC 114 15 1 Overview 114 15 2 Operation 115 15 3 Registers 116 16 LEON3 FT...

Page 4: ...s 168 21 4 Memory EDAC 168 21 5 Bus Ready signalling 169 21 6 Access errors 171 21 7 Registers 172 22 Fault Tolerant NVRAM Memory Interface 176 23 MIL STD 1553B AS15531 Interface 177 23 1 Overview 177...

Page 5: ...29 3 Pulse command 264 29 4 Pulse sequencer 264 29 5 Pulse sampler 266 29 6 Registers 266 30 Pulse Width Modulation Generator 277 30 1 Overview 278 30 2 Operation 278 30 3 Registers 280 31 PacketWire...

Page 6: ...Registers 372 37 I2C to AHB bridge 376 37 1 Overview 376 37 2 Operation 377 37 3 Registers 381 38 I2C master 384 38 1 Overview 384 38 2 Operation 385 38 3 Registers 388 39 I2C slave 391 39 1 Overview...

Page 7: ...67 47 2 Operation 468 47 3 Registers 468 47 4 Example of configure and use the Memory protection 484 48 Serial Debug and remote access Interface 486 48 1 Overview 487 48 2 Operation 487 48 3 Registers...

Page 8: ...teristics 519 52 8 ADC Electrical Characteristics 520 52 9 Reference Voltages and Currents Electrical Characteristics 524 52 10 Reset and Brownout Detector Electrical Characteristics 524 52 11 AC char...

Page 9: ...et Shipping space grade product 1 3 Updates and feedback Feedback can be sent to Cobham Gaisler AB support support gaisler com 1 4 Software support The GR716 LEON3FT microcontroller design is supporte...

Page 10: ...M May 2019 Version 1 29 10 www cobham com gaisler GR716 1 6 Document revision history Change record information is provided in table 1 Table 1 Change record Version Date Note 1 29 May 2019 First publi...

Page 11: ...O First In First Out refers to buffer type FPU Floating Point Unit Gb Gigabit 109 bits GB Gigabyte 109 bytes GiB Gibibyte gigabinary byte 230 bytes unit defined in IEEE 1541 200 I O Input Output ISR I...

Page 12: ...The least significant bit of a data type has the rightmost position Unless otherwise indicated the MSb of a data type has the highest bit number and the LSb the lowest bit number 1 8 2 Radix The foll...

Page 13: ...2 EF2 Field description 15 8 Example field 1 EF1 Field description 7 0 Example field 0 EF0 Field description Table 4 Reset value definitions Value Description 0 Reset value 0 1 Reset value 1 Used for...

Page 14: ...he AMBA Advanced High speed Bus AHB to which the LEON3FT processor and other high bandwidth units are connected Low band width peripherals functions are connected to the AMBA Advanced Peripheral Bus A...

Page 15: ...support up to 16 MB ROM and 256 MB SRAM Support for package option with embedded SRAM PROM FTMCTRL Scrubber with programmable scrub rate for all embedded memories and external PROM SRAM and SPI memori...

Page 16: ...ferential or eight single ended Analog to Digital Converters ADC 11 bit at 200KS s with programmable pre amplifier and support for oversampling Dual sample and hold circuit integrated for simultaneous...

Page 17: ...t from redundant memory Fast boot option System configuration Reset and boot status Individual reset and clock control for digital and analog peripherals Remote reset and boot control Clock source and...

Page 18: ...EU protection of register file with zero impact on software timing and hardware multiply and divide units The multiplier is a 16x16 hardware multiplier that is iterated four times Floating point opera...

Page 19: ...tem have the same latency and behav iour in the corrected as in the uncorrected case This also applies to the CPU so dynamic SEU han dling schemes such as the LEON3FT pipeline restart on error options...

Page 20: ...microcon troller design that do not have an internal DMA engine The DMA controller can be programmed to initiate DMA transfers on events such as interrupts to the GRDMAC core to achieve timely readout...

Page 21: ...nal bootstrap signals Based on these signals the processor performs tasks such as load software to internal RAM from an external memory device enable remote access via SpaceWire SPI UART or I2C See se...

Page 22: ...d to be functional directly after the micro controller leaves reset no initialisation from the processor is required The communication links can also be disabled by the processor a feature that can be...

Page 23: ...ller have one dedicated Serial Debug interface The Serial Debug unit is directly connected to the AMBA debug bus The Serial Debug unit have a unique AMBA address described in chapter 2 11 The debug in...

Page 24: ...ity The inter nal interrupt bus distributes all 64 unique inter rupts IDs in table 29 The interrupt bus is used to program event driven functions e g the DMA channel 0 to respond to a specific Inter r...

Page 25: ...quest for reset of MIL 1553B interface support TDP MIL 1553B and SpaceWire Internal bus for communication between the SpaceWire Time Distribution Protocol core and the SpaceWire interface or the MIL 1...

Page 26: ...w There is also a reset release delay at power up starting to count when VDD_CORE goes above its reset threshold level The Brownout detectors are intended to be used as pre warnings to the GR716 micro...

Page 27: ...chip Therefore no fast load current steps are present in any of the on chip blocks using this supply It is essential that especially this supply has good PCB decoupling filtering across VDDA_REF and V...

Page 28: ...ent 12bit 3MSps DAC blocks The DAC output is a sourcing current single ended output typically to be loaded by virtual ground generated by an op amp on PCB or by a pas sive impedance connected to PCB g...

Page 29: ...ure protection is desired the user needs to measure the sensor and take adequate actions in the system application at hand 2 3 9 Core Voltage VDD_CORE Monitor The core voltage level can be monitored v...

Page 30: ...s until programmed otherwise Configuration and assigning of functions to external I O is flexible and is controlled by software via registers described in section 7 1 Figure 5 shows an overview of how...

Page 31: ...MEM_ADDR15 CAN_SEL0 SPI_MOSI1 ADCDAC_D2 PWM15 SYS CFG GP2 GPIO16 UART_RX3 MEM_ADDR16 CAN_RX1 SPI_SEL1 ADCDAC_D3 GPIO17 UART_RTSN4 MEM_ADDR17 CAN_TX1 SPI_SLV1_0 ADCDAC_A0 GPIO18 UART_TX4 MEM_ADDR18 CAN...

Page 32: ...MEM_ADDR20 I2CS_SCL2 SPI_SEL1 ADCDAC_D1 PWM1 SPIM_SCK1 AHBUART_RX TDP_E_ET_I GPIO51 UART_RX0 MEM_ADDR21 1553_RXENA SPI_MOSI1 ADCDAC_D2 PWM2 SPIM_MOSI1 TDP_PULSE0 GPIO52 UART_CTSN1 MEM_ADDR22 1553_TXA...

Page 33: ...escription LVDS_RX 1 RXD SpaceWire receiver data interface LVDS_RX 2 RXS SpaceWire receiver strobe interface LVDS_TX 0 TXD SpaceWire transmitter data interface LVDS_TX 1 TXS SpaceWire transmitter stro...

Page 34: ...ISO MISO SPI Memory master input slave output GPIO 2 MOSI Redundant SPI Memory master output slave input GPIO 1 SCK Redundant SPI Memory master clock output GPIO 0 SEL Redundant SPI Memory slave selec...

Page 35: ...Chip Select Note 1 Interface uses CMOS type interface Table 14 PROM FLASH memory pin configurations Pin Name Interface Name Functional description GPIO 0 ADDR 0 Memory address interface GPIO 1 ADDR 1...

Page 36: ...ption is given to the designer to assign the extra pin to another system interface 2 7 2 External Memory interface The external PROM SRAM interface occupies many external I Os due parallel data and ad...

Page 37: ...icrocontroller as described in table 2 6 Each functional group maps individ ual functional pins to physical external pins Example of UART0 configuration description are shown in table 16 Table 16 spec...

Page 38: ...he system using with SpaceWire 1 UART and external SPI memory Table 18 Example of executing I O configuration script grmon2 source iomx tcl grmon2 gen_config iomx_uart0_cfg grmon2 Table 19 Example of...

Page 39: ...figuration 2 8 6 Validation of custom pin configuration The supplied validation scripts contains variables for valid pin placement of each interface specified in table 2 6 See script for valid names 2...

Page 40: ...The columns marked with namn index are a combined user scenarios and gives the fixed functions and pins for the scenario Empty entries in columns marked with namn index indicates that the user can as...

Page 41: ...SYS CFG GP3 GP1 MEM_DATA0 MEM_DATA0 MEM_DATA0 MEM_DATA0 MEM_DATA0 MEM_DATA0 SYS CFG GP3 GP2 MEM_DATA1 MEM_DATA1 MEM_DATA1 MEM_DATA1 MEM_DATA1 MEM_DATA1 SYS CFG GP3 GP3 MEM_DATA2 MEM_DATA2 MEM_DATA2 M...

Page 42: ...emory should be used in order to utilize the pins on the device more efficiently For this example we assume at least 256KiB is needed Boot from external PROM is required Connects to spacecraft bus eit...

Page 43: ...P2 GP7 ROM_CSN0 SPW_TXS SYS CFG GP3 GP0 ROM_CSN1 SPW_TXD SYS CFG GP3 GP1 MEM_DATA0 MEM_DATA0 SYS CFG GP3 GP2 MEM_DATA1 MEM_DATA1 SYS CFG GP3 GP3 MEM_DATA2 MEM_DATA2 SYS CFG GP3 GP4 MEM_DATA3 MEM_DATA3...

Page 44: ...he following assumptions are made for the system System boots and runs software from external serial memory Software can also execute from internal instruction memory Connects to spacecraft bus either...

Page 45: ...3 GP5 SYS CFG GP3 GP6 SYS CFG GP3 GP7 SYS CFG GP4 GP0 SYS CFG GP4 GP1 SYS CFG GP4 GP2 SYS CFG GP4 GP3 SYS CFG GP4 GP4 SYS CFG GP4 GP5 1553_RXENA 1553_RXENA SYS CFG GP4 GP6 1553_TXA 1553_TXA SYS CFG GP...

Page 46: ...R1553B MIL STD 1553B AS15531 interface 0x01 0x04D GRADCDAC ADC DAC Interface 0x01 0x036 GRCAN CAN 2 0 controller with DMA 0x01 0x03D GRCLKGATE Clock gating unit 0x01 0x02C GRDMAC DMA Controller with i...

Page 47: ...000000 0x800000FF Memory controller with EDAC No DLRAM 0x80001000 0x800010FF On chip Data memory control registers No IRQAMP 0x80002000 0x800023FF Multi processor Interrupt Ctrl No GPTIMER 0x80003000...

Page 48: ...ceiver with DMA No PWTX 0x8010F000 0x8010F0FF PacketWire Transmitter with DMA No A P B C T R L 2 APBUART 1 0x80300000 0x803000FF Generic UART 0 Yes APBUART 1 0x80301000 0x803010FF Generic UART 1 Yes A...

Page 49: ...DC 1 0x80406000 0x804060FF On chip ADC interface 6 Yes ADC 1 0x80407000 0x804070FF On chip ADC interface 7 Yes DAC 1 0x80408000 0x804080FF On chip DAC interface 0 Yes DAC 1 0x80409000 0x804090FF On ch...

Page 50: ...a memory A P B C T R L D B G AHBUART 0x94000000 0x940000FF AHB Debug UART Yes L3STAT 0x94001000 0x940013FF LEON3 Statistics Unit Yes GRGPREG 0x94002000 0x940020FF Analog test control Yes 0x94003000 0x...

Page 51: ...0x8 i e local write address in processor data memory or APB peripheral needs to be modified in order to avoid exception from the LEON3FT processor The shifted address is automatically decoded in the l...

Page 52: ...R0 Interrupt 2 from timer block 0 11 11 GPTIMER0 Interrupt 3 from timer block 0 12 12 GPTIMER0 Interrupt 4 from timer block 0 13 13 GPTIMER0 Interrupt 5 from timer block 0 14 14 GPTIMER0 Interrupt 6 f...

Page 53: ...I controller 0 12 49 SPICTRL Interrupt from SPI controller 1 13 50 I2CM Interrupt from I2C master controller 0 14 51 I2CM Interrupt from I2C master controller 1 2 52 SPIMCTRL Interrupt from SPI memory...

Page 54: ...he processor will start execute from software from address selected by bootstrap signals SPIM_MOSI SPIM_SCK SPIM_SEL GPIO 0 Determines the use of EDAC for external boot RAM when the GR716 microcontrol...

Page 55: ...r A weak resistor is defined as resistor which require low current from the drive circuitry The resistance should be greater or equal to 10K ohm Note 2 Bootstrap signals determine state of GR716 micro...

Page 56: ...10 MHz input clock after initialization of the pro cessor high low high low high low low high Enable SpaceWire remote access using a 10 MHz input clock after initialization of the pro cessor and inter...

Page 57: ...x 2 x 2 low high Enable UART remote access after initialization of the processor and internal memory test Note 1 To enable remote access SPIM_MOSI must be bootstrapped to high Note 2 Configuration pi...

Page 58: ...SPI memory with DMR protection boot after ini tialization of the proces sor Processor will copy and extract ASW con tainer before executing application software Note 1 To enable external memory acces...

Page 59: ...rnal ASW SRAM memory with DMR protection boot after initialization of the processor Processor will copy and extract ASW container before execut ing application software Note 1 To enable external memor...

Page 60: ...Enable external ASW PROM FLASH memory with DMR protection boot after initialization of the processor Processor will copy and extract ASW container before executing application software Note 1 To enab...

Page 61: ...pplication software low high high high high 5 low 7 Enable external ASW I2C memory with DMR protection boot after ini tialization of the proces sor Processor will copy and extract ASW con tainer befor...

Page 62: ...UART transmit data Yes Out DUART_RXD Debug UART receive data Yes In SPIM_MOSI SPI Memory master output slave input Yes Out SPIM_SCK SPI Memory master clock output Yes Out SPIM_SEL SPI Memory slave sel...

Page 63: ...e No Analog RREF External BandGap reference Connect to ground via resistance of 5 11 Kohm No Analog LDO_IN LDO voltage supply No Analog VDDIO1 Digital IO supply No Analog VDD1 Core supply No Analog GN...

Page 64: ...PLL can be used to generate frequencies required for SpaceWire 1553B or the system The lowest frequency to be used with the integrated PLL is 4 MHz to be able to meet jitter performance for SpaceWire...

Page 65: ...ternal sources see figure 5 and section 10 Clock source and divisor is selected via con figuration registers described in section 10 The clock source and divisor needs to be chosen carefully depended...

Page 66: ...ck to use the default system input clock during reset and if the system tries to switch to a disabled clock source 4 4 SpaceWire clock The clock used for the SpaceWire link receiver and transmitter lo...

Page 67: ...lock gating unit through which individual cores can have their clocks enabled dis abled and resets driven The LEON3 processor core will automatically be clock gated when the processor enters power dow...

Page 68: ...microcontroller or via remote accesses via UART I2C SPI CAN MIL STD 1553B or SpaceWire interface Remote access via CAN and MIL STD 1553B requires external boot ram For more information about individu...

Page 69: ...tion set architecture The LEON3FT processor used in this design implements the SPARC V8 instruction set architecture This means that any compiler that produces valid SPARC V8 executables can be used F...

Page 70: ...up configuration for GPIO 0 to 31 SYS CFG PULLUP0 0x8000D024 System IO Pullup configuration for GPIO 32 to 64 SYS CFG PULLUP1 0x8000D028 System IO Pulldown configuration for GPIO 0 to 31 SYS CFG PULLD...

Page 71: ...r GPIO pin 22 For functionality see Table 2 6 23 20 GPIO21 functional select GP5 Select functionality for GPIO pin 21 For functionality see Table 2 6 19 16 GPIO20 functional select GP4 Select function...

Page 72: ...for GPIO pin 46 For functionality see Table 2 6 23 20 GPIO45 functional select GP5 Select functionality for GPIO pin 45 For functionality see Table 2 6 19 16 GPIO44 functional select GP4 Select funct...

Page 73: ...2 6 Table 47 0x8000D020 SYS CFG PULLUP0 System GPIO pullup configuration register for GPIO 0 to 31 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 UP 0x00000000...

Page 74: ...ver disable 15 12 LVDS Reciever 0 RX0 Select functionality for LVDS receiver 0 0x8 LVDS receiver disable 11 8 LVDS Transmitter 2 TX2 Select functionality for LVDS transmitter 2 0x1 SPI for Space Slave...

Page 75: ...wc wc 31 2 Not used 1 Multiple error interrupt M 0 Single Error interrupt E Table 54 0x8000D03C SYS CFG ESTAT System IO configuration status protection register 31 30 29 28 27 26 25 24 23 22 21 20 19...

Page 76: ...uring initialization all states up to and including the connecting state For more information see 33 3 5 Default settings is determined by GPIO 63 and DUART_TX For more information see table 30 in sec...

Page 77: ...PLL_LOCK output on internal analog test bus 4 29 Enable PLL_OUT output on internal analog test bus 5 output on internal analog test bus 4 28 Enable VMON33LVDS_BG33_OK output on internal analog test bu...

Page 78: ...external resistor reference sel_VMON18_INT_COMPIN for VMON18 1 21 Select external resistor reference sel_VMON33_INT_COMPIN5 for VMON33 5 20 Select external resistor reference sel_VMON33_INT_COMPIN4 f...

Page 79: ...d mode active high input GPIO 7 6 ADC Pre AMP Pair select input GPIO 9 8 ADC Pre AMP Gain select input GPIO 10 ADC Pre AMP Cross GPIO 11 ADC Pre AMP Select On Chip Temperature sensor GPIO 22 12 ADC di...

Page 80: ...SU3 DSU2 DSU1 DSU0 RW1 RW0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 31 30 On chip data memory test control bits DM 0x0 Not used M...

Page 81: ...Not used Table 63 Memory test status register AMBA address Register Acronym 0x8000E004 Status register for memory test SYS STAT MEMTEST Table 64 0x8000E004 SYS STAT MEMTEST Memory test status register...

Page 82: ...esult 13 12 11 10 9 8 7 6 5 4 3 2 LEON3FT register Window 1 memory RW1 0x0 No error detected during last test If test has been run 0x1 Enable March C test algorithm 0x2 Error during last scan 0x3 Inva...

Page 83: ...xternal loop back mode routed back via rising or falling edge clocked flip flops SpaceWire External loop back means that the external SpaceWire I O pins are routed via SpaceWire Phy to the correspondi...

Page 84: ...sed before it goes high The internal reset signal and the external reset input signal RESET_IN_N input are asynchronous However note that the reset of all internal Microcontroller logic is synchronous...

Page 85: ...s set to enable 8 2 3 Reset IO control The 64 General purpose IO described in chapter 2 4 and 2 5 is forced to high impedance mode when core voltage supply is lower than the threshold for releasing th...

Page 86: ...2 1 0 RESERVED BI BC BA BD BB BL BP 0x00000000 0 0 0 0 0 0 0 r r r r r r r r 31 7 RESERVED 6 Brown Out Detected BI Faulty 3 3 V power supply detected 5 Brown Out Detected BC Faulty 1 8 V power supply...

Page 87: ...n 2 Interrupt Mask for Brown Out Detection MB Set to 0 to mask interrupt generation for faulty BandGap power supply detection interrupt from Brown Out detection 1 Interrupt Mask for Brown Out Detectio...

Page 88: ...Out Powerdown BB Powerdown BandGap power supply 1 Brown Out Powerdown BL Powerdown LVDS power supply detected 0 Brown Out Powerdown BP Powerdown PLL power supply detected Table 75 0x20 XEN Power contr...

Page 89: ...e XO block requires an external crystal on PCB parallel resonant fundamental tone AC cut XTAL The XTAL two terminals are to be connected directly to the two external XO pins and a capacitor to ground...

Page 90: ...0 10 FU WA LF 20MHz 2 Note 1 The total crystal load capacitance should take into account the PCB stray capacitance and the input capacitance of the GR716 device on XO pins to ground The XO input pins...

Page 91: ...input The PLL reference clock input is allowed to be asynchronous to any other clocks in the GR716 LEON3FT microcontroller 10 2 2 Detailed description For more information about using the PLL in the...

Page 92: ...en to 1 the PLL is powerdown The PLL should always be in power down mode when not used i e when the PLL is bypassed 30 3 RESERVED 2 0 PLL configuration CFG Internal PLL multiplier depended upon the in...

Page 93: ...alues will result in the external signal SYS_CLK to be used as reference This register can be changed after reset due to bootstrap pins 7 0 Not used Table 82 0x0C SPWREF Select reference for SpaceWire...

Page 94: ...y by 44 0x18 Divide input frequency by 48 0x1A Divide input frequency by 52 0x1C Divide input frequency by 56 0x1E Divide input frequency by 60 All other combinations is not valid When bitfield DUTY p...

Page 95: ...y of the total clock cycles specified in the DIV bitfield the generated clock shall be high IF this register is set to 0x0 the duty cycle will be set to clock cycles defined in DIV and the clock perio...

Page 96: ...or PLL SPW or 1553B clock configuration registers 17 16 Enable error interrupt generation EIRQ Register for enabling error interrupt generation b00 No interrupt generation b11 Enable interrupt generat...

Page 97: ...duty cycle defined in the DUTY bitfield Table 90 0x2C PWM1REF Select reference for PWM1 clock 31 24 23 16 15 10 9 8 7 0 RESERVED D2 DUTY RESERVED SEL DIV 0x0 0x0 0x0 0 0 r rw r rw rw 31 25 RESERVED 2...

Page 98: ...he internal voltage reference output pin VREF This decoupling capacitance should be 4 7nF located very close to the VREF pin and grounded very close to the VSSA_REF pin There should be no other compon...

Page 99: ...shows memory locations and functions used for ADC configuration and control The primary clock gating unit GRCLKGATE described in section 26 is used to enable disable indi vidual ADC converters and ADC...

Page 100: ...ntroller to support different complex sampling modes over multiple ADC channels The digital interface also supports sampling modes to suppress noise and to increase the resolution and ENOB Increasing...

Page 101: ...k needs to be disabled and the IOs next to the ADC inputs pins needs to be silent The system software needs to program the ADC to trigger and sample an input using an external or internal trigger whil...

Page 102: ...AS 0x1 Start sampling i e listen for sync defined in sync register This will generate a new interrupt and temperature reading from e g an external temperature sensor once every second with 14 bit reso...

Page 103: ...descriptor 0 Transfer 8 samples and configure re try to 8 0x3000101C 0x80005A5A M2B conditional descriptor 0 Protection bits for checking DMA descriptor 0x30001020 0x00000002 M2B data descriptor 0 nex...

Page 104: ...he user application shall Enable ADC clock for channel to use Disable all other interfaces or peripherals not needed in the clock gating unit Enable interrupt generation in ADC or if the DMA is used t...

Page 105: ...etection register 0x24 Low range detection register 0x2C 0x38 Sequence Sampling memory register s Add offset n 0x100 to APB address offset in table for accessing ADC controller n Table 94 0x00 ACFG AD...

Page 106: ...ol bits can be combined in order to sample the ADC channel E g setting the bit field ASAMPC AE 4 and ASAMPC AO 255 will store 4 samples with the oversampling ratio of 256 for the selected ADC channel...

Page 107: ...r 6 6 Synchronize ADC to Timer unit 0 counter 5 5 Synchronize ADC to Timer unit 0 counter 4 4 Synchronize ADC to Timer unit 0 counter 3 3 Synchronize ADC to Timer unit 0 counter 2 2 Synchronize ADC to...

Page 108: ...4 3 2 1 0 RESERVED MS MH ML ME 0x00000000 0 0 0 0 r wc rw rw rw 31 4 RESERVED 3 Interrupt Mask for ADC End of sequence MS 2 Interrupt Mask for ADC High level detection MH 1 Interrupt Mask for ADC Low...

Page 109: ...his register Note To make use of this function the AD C must be enable the ACFG AH bit must set Table 104 0x2C 0x38 ASQ ADC Sequence status register 0 1 2 and 3 31 19 18 0 Reserved AD 0 r rw 31 19 RES...

Page 110: ...er capac itor is needed for damping and decoupling of lower frequencies which typically is a tantalum capaci tor in the order of 100uF and ESR in the order of 0 1ohm The LDO will cause additional on c...

Page 111: ...sible externally 14 2 2 Detailed description The temperature sensor output signal is a monotonic voltage signal versus temperature It is measured by the ADC in the same way as any other analog MUX cha...

Page 112: ...be used to perform reset of individual DAC units Software must enable clock and release reset described in section 26 before DAC configuration and transmission can start External IO selection per DAC...

Page 113: ...sed the DAC output level or value will not be updated or changed until an event has occurred on the selected trigger The trigger event can be programmed to also generate an interrupt when a new value...

Page 114: ...0MHz and samples rate 1Msps the scaler should be set to 50 15 7 Reserved 7 4 DAC Conversion interrupt delay DC Number of DAC clock cycle for digital to analog conversion Each sample requires 14 sample...

Page 115: ...ynchronize GPIO n to Timer unit 1 counter 4 12 Synchronize GPIO n to Timer unit 1 counter 3 11 Synchronize GPIO n to Timer unit 1 counter 2 10 Synchronize GPIO n to Timer unit 1 counter 1 9 Synchroniz...

Page 116: ...12 0x14 DINT DAC Interrupt Register 31 1 0 Reserved EI 0x00000000 0 r wc 31 1 Reserved 0 Interrupt for DAC End of conversion EM Table 113 0x18 DMASK DAC Interrupt Mask Register 31 1 0 Reserved EM 0x00...

Page 117: ...FPU The floating point pro cessors execute in parallel with the integer unit and does not block the operation unless a data or resource dependency exists 16 1 3 On chip debug support The LEON3 pipelin...

Page 118: ...ts a power down mode which halts the pipeline until the next interrupt The processor also supports clock gating during the power down period A small part of the CPU is always awake and needs to run du...

Page 119: ...ALU logical and shift operations are performed For memory operations e g LD and for JMPL RETT the address is generated 5 ME Memory Data memory is read or written at this time 6 XC Exception Traps and...

Page 120: ...ad delay or interlock delays FPU Coprocessor The floating point unit or coprocessor may need to hold the pipeline or extend a specific instruction When this is done is specific to the FP CP unit 16 2...

Page 121: ...ge can be watched for instruction or data access and on a breakpoint hit trap 0x0B is generated 16 2 8 Instruction trace buffer The instruction trace buffer consists of a circular buffer that stores e...

Page 122: ..._detected 0x0B 7 Hardware breakpoint match Precise window_overflow 0x05 8 SAVE into invalid window Precise window_underflow 0x06 8 RESTORE into invalid window Precise r_register_access_error 0x20 9 re...

Page 123: ...ter window used for reading writing non global registers is taken from the AWP register field instead of the normal CWP register field and SAVE and RESTORE operations modify the AWP field instead of t...

Page 124: ...ill be fetched prior to fetching the trap handler 16 2 17 Processor reset operation The processor is reset by asserting the RESET input for at least 4 clock cycles The following table indicates the re...

Page 125: ...interrupt request as soon as possible If the counter is set to a specific value depending on the timing of the memory system then it can enable the zero jitter behavior to force the interrupt latency...

Page 126: ...aisler s GRFPU Lite is connected with the LEON3 pipeline The characteristics of the FPU s are described in the next sections 16 4 1 GRFPU Lite GRFPU Lite is a smaller version of GRFPU suitable for imp...

Page 127: ...to indicate if the accesses is instruction or data and if it is a user or supervisor access In case of atomic accesses a locked access will be made on the AMBA bus to guarantee atomicity as seen from...

Page 128: ...rdwired to 0011 3 for LEON3 23 20 Integer condition codes ICC see sparcv8 for details 19 14 Reserved 13 Enable coprocessor EC always set to 0 to indicate no coprocessor available in microcontroller 12...

Page 129: ...ot used 24 23 REX version REXV REX version 22 21 REX mode REXM set to 00 for REX enabled 01 for REX illegal and 10 for REX transpar ent mode Writable with reset value 01 when REX support has been enab...

Page 130: ...STWIN Starting window of partition 20 16 Maximum value of current window pointer CWPMAX Partition size minus 1 Reset value is number of windows minus 1 which with STWIN 0 maps whole register file int...

Page 131: ...and for all processors connected to the same debug support unit The time tag counter will increment when any of the trace buffers is enabled or when the time tag counter is forced to be enabled via th...

Page 132: ...break on instruction fetch from the specified address mask combination DL break on data load from the specified address mask combination DS break on data store to the specified address mask cominatio...

Page 133: ...eld to indicate FT values higher than 3 17 FPU RF Test Enable Enables FPU register file test mode Parity bits are xored with TB before writ ten to the FPU register file 16 FP RF protection disable FDI...

Page 134: ...nitialized This means that access to an un initialized un written general purpose register could cause a register access trap tt 0x20 Such behavior is considered as a software error as the soft ware s...

Page 135: ...d formats are single and double precision floating point numbers The floating point unit is not pipelined and executes one floating point operation at a time 17 2 Functional Description 17 2 1 Floatin...

Page 136: ...OD INT SP DP NX Integer to floating point conversion FSTOI FDTOI SP DP INT NV NX Floating point to integer conversion The result is rounded in round to zero mode FSTOD FDTOS SP DP DP SP NV NV OF UF NX...

Page 137: ...andard This includes detec tion of Invalid Operation NV Overflow OF Underflow UF Division by Zero DZ and Inexact NX exception conditions Generation of special results such as NaNs and infinity is also...

Page 138: ...section 26 is used to enable disable indi vidual UART units The unit GRCLKGATE can also be used to perform reset of individual UART units Software must enable clock and release reset described in sec...

Page 139: ...ready to transmit data is transferred from the transmitter FIFO to the transmitter shift register and converted to a serial stream on the transmitter serial output pin TXD It automatically sends a st...

Page 140: ...e FIFO which is identical to the one in the transmitter During reception the least significant bit is received first The data is then transferred to the receiver FIFO and the data ready DR bit is set...

Page 141: ...RF the receiver is enabled and the FIFO is half full The interrupt signal is continuously driven high as long as the receiver FIFO is half full at least half of the entries contain data frames Note th...

Page 142: ...gister UART2 DATA 0x80302004 UART2 Status register UART2 STATUS 0x80302008 UART2 Control register UART2 CTRL 0x8030200C UART2 Scaler register UART2 SCALER 0x80302010 UART2 FIFO debug register UART2 FI...

Page 143: ...cates that the Receiver FIFO is full Reset 0 9 Transmitter FIFO full TF indicates that the Transmitter FIFO is full Reset 0 8 Receiver FIFO half full RH indicates that at least half of the FIFO is hol...

Page 144: ...applicable if receiver interrupt enable is set See section 18 6 for more details 12 Break interrupt enable BI When set an interrupt will be generated each time a break character is received See sectio...

Page 145: ...an be accessed at any time while the processor registers and trace buffer can only be accessed when the processor has entered debug mode In debug mode the processor pipeline is held and the processor...

Page 146: ...ter and address consisting of 20 LSB bits of the original address 19 3 AHB trace buffer The AHB trace buffer consists of a circular buffer that stores AHB data transfers the monitored AHB bus is eithe...

Page 147: ...set The values of the LD and ST fields of this register has no effect on filtering 19 3 2 AHB statistics The DSU generates statistics from the traced AHB bus Statistics is collected and output to LEON...

Page 148: ...register 31 28 as defined in the table below spdel SPLIT delay Active during the time a master waits to be granted access to the bus after reception of a SPLIT response The core will only keep track...

Page 149: ...alternate space 0xE SPARC Format 3 LOAD or STORE instructions to alternate space 0x80 0xFF Table 140 DSU memory map Address offset Register 0x000000 DSU control register 0x000008 Time tag counter 0x00...

Page 150: ...mode PE returns 1 on read when processor is in error mode else 0 If written with 1 it will clear the error and halt mode 8 External Break EB Value of the external DSUBRE signal read only 7 External En...

Page 151: ...step SSx if set the processor x will execute one instruction and return to debug mode The bit remains set after the processor goes into the debug mode As an exception if the instruction is a branch w...

Page 152: ...n to 1 it will have the same effect on the AHB trace buffer as if HREADY was asserted on the bus at the same time as a sequential or non sequential transfer is made This means that setting this bit to...

Page 153: ...9 7 8 AHB trace buffer index register The AHB trace buffer index register contains the address of the next trace line to be written Table 148 0x000044 ATBI AHB trace buffer index register 31 4 3 0 IND...

Page 154: ...ggers if a specified master performs an access to a spec ified slave 11 10 RESERVED 9 8 AHB breakpoint filtering BPF Bit 9 of this field applies to AHB breakpoint 2 and bit 8 applies to AHB breakpoint...

Page 155: ...on data store address Table 153 0x110000 ITBCO Instruction trace control register 0 31 29 28 16 15 0 RESERVED ITPOINTER 0 NR r rw 31 28 Trace filter configuration 27 16 RESERVED 15 0 Instruction trace...

Page 156: ...ia the DMAAMBA interface The processor interface and priority scheme guar antees single cycle instruction and data execution in the LEON3FT processor The instruction and data memory implements a contr...

Page 157: ...rt and the CPU port When the CPU port performs a read to a specific address a write on the AHB port to the same address is stalled until the CPU read has completed This feature is enabled by the LRAMC...

Page 158: ...etween each scrubbing access Wash The scrubber can be configured to wash the memory writing to all memory location and generate valid checksums This is done by setting then SCRUBCFG WASH field to 1 To...

Page 159: ...1 LRAMCFG 0x8000B004 Instruction memory Scrubber data AHBRAM1 SCRUBDATA 0x8000B008 Instruction memory Scrubber control AHBRAM1 SCRUBCTRL 0x8000B00C Instruction memory Scrubber configuration AHBRAM1 SC...

Page 160: ...E N 0 0 0 rw rw rw 31 2 ADDR Scrubber address offset 1 PEN Scrub access pending 0 SEN Scrubber enable Table 159 0x8000100C AHBRAM0 SCRUBCFG Scrubber Configuration Register 31 16 15 14 13 12 11 10 4 3...

Page 161: ...the AHB port to the same address as the access on the CPU port is stalled 12 IE Interrupt enable Enable the assertion of an interrupt when the scrubber detects a un correctable error 11 10 ACOR Auto c...

Page 162: ...B W A S H 0 0 0 0 0 0 0 0 0 0 rw r rw rw rw rw rw rw rw rw 31 16 DELAY Scrubber delay Delay in clock cycles between each scrub access 15 14 Reserved 13 DISW Disable the scrubber after the wash operati...

Page 163: ...figuration registers are located on APB bus in the address range from 0x80000000 to 0x80000FFF See fault tolerant 8 bit memory controller unit con nections in the next drawing The drawing picture memo...

Page 164: ...EDAC check bits are latched on the rising edge of the clock on the last data cycle On non consecutive accesses a idle cycle is placed between the read cycles to prevent bus contention due to slow turn...

Page 165: ...two waitstates data1 data2 address romsn data oen cb data2 data clk A1 D1 CB1 data2 Figure 22 Prom write cycle 0 waitstates data address romsn data rwen cb lead out clk A1 D1 CB1 lead in Figure 23 Pro...

Page 166: ...essary bytes will be written All possible combinations of width EDAC and RMW are not supported The supported combina tions are given in table 164 and the behavior of setting an unsupported combination...

Page 167: ...For the ROM the EDAC protection is provided in a similar way as for the SRAM memory described above The difference is that write accesses are not being handled automatically Instead write accesses mu...

Page 168: ...least one additional cycle from when BRDYN is first asserted until it is visible internally In figure 26 one cycle is added to the data2 phase Figure 25 READ cycle with one extra data2 cycle added wit...

Page 169: ...nal for read and write accesses For reads it is sampled together with the read data For writes it is sampled on the last rising edge before chip select is de asserted which is controlled by means of w...

Page 170: ...le 166 0x00 MCFG1 Memory configuration register 1 31 30 29 28 27 26 25 24 23 20 19 18 17 R PBRDY ABRDY RESERVED R BEXCN R RESERVED IOEN R ROMBANKSZ 0 0 0 NR 0 0 0 0XF 0 0 0x0 r rw rw rw rw rw r rw rw...

Page 171: ...t field shall always be set to 00 7 4 PROM write waitstates PROM WRITE WS Sets the number of wait states for PROM write cycles 0000 0 0001 2 0010 4 1111 30 3 0 PROM read waitstates PROM READ WS Sets t...

Page 172: ...dicates if memory EDAC is present read only 26 12 RESERVED 11 EDAC diagnostic write bypass WB Enables EDAC write bypass 10 EDAC diagnostic read bypass RB Enables EDAC read bypass 9 RAM EDAC enable RE...

Page 173: ...7 ROM lead out ROMHWS Lead out cycles added to ROM accesses are ROMHWS 3 0 2ROMHWS 6 4 6 0 RESERVED Table 171 0x14 MCFG6 Memory configuration register 6 31 16 RESERVED 0 r 15 14 13 7 6 0 RESERVED RAMH...

Page 174: ...vailable to access in package embedded memory The LEON3FT microcontroller support up to four chip selects using this type of memory The memory controller interface is not available on external pins on...

Page 175: ...and transmission can start External IO selection per GR1553B unit is made in the system IO configuration register GRG PREG in the address range from 0x8000D000 to 0x8000D03F See section 7 1 for furthe...

Page 176: ...mit RT to RT transfer Broadcast BC to RTs Broadcast RT to RTs Each transfer can contain 1 32 data words of 16 bits each The bus controller can also send mode codes to the RTs to perform administrative...

Page 177: ...t of shared registers Some of the control register fields for the BC and RT are protected using a key a field in the same register that has to be written with a certain value for the write to take eff...

Page 178: ...edule s timers will be reset When the extsync bit is set in the schedule s next transfer descriptor the core will wait for a positive edge on the external sync input before starting the command The sc...

Page 179: ...mmand descriptors always generate interrupts and stop the schedule Before a transfer triggered interrupt is generated the address to the corresponding descriptor is written into the BC transfer trigge...

Page 180: ...is set store the opposite bus instead only if the per RT bus mask is supported in the core See section 23 4 3 for more information 18 Extended intermessage gap GAP If set adds an additional amount of...

Page 181: ...oop back check failure Error code 011 is issued only when the number of data words match the success case otherwise code 100 is used Error code 011 can be issued for a correctly executed transmit last...

Page 182: ...h 30 27 Reserved Set to 0 26 Interrupt if condition met IRQC 25 Action ACT What to do if condition is met 0 Suspend schedule 1 Jump 24 Logic mode MODE 0 Or mode any bit set in RT2CC RTCC is set in RT2...

Page 183: ...nment When the RT receives a data transfer request it checks in the subaddress table that the request is legal If it is legal the transfer is then performed with DMA to or from the corresponding data...

Page 184: ...can not be logged or disabled No Yes 3 00011 Initiate self test No built in action Yes No 21 18 4 00100 Transmitter shutdown The RT will stop responding to commands on the other bus not the bus on wh...

Page 185: ...to indicate invalid pointer R W 0x10 N 0x0C Unused Note The table entries for mode code subaddresses 0 and 31 are never accessed by the core 31 19 18 17 16 15 14 13 12 8 7 6 5 4 0 0 reserved WRAP IGN...

Page 186: ...tting the IGNDV bit in the subaddress table 30 IRQ Enable override IRQEN Log and IRQ after transfer regardless of SA control word settings Can be used for getting an interrupt when nearing the end of...

Page 187: ...itself 23 6 3 No response handling In the MIL STD 1553B protocol a command word for a mode code using indicator 0 or a regular transfer to subaddress 8 has the same structure as a legal status word Th...

Page 188: ...e table 188 0xC0 0xFF BM Register area see table 189 May differ depending on core configuration Table 187 MIL STD 1553B interface BC specific registers APB address offset Register R W Reset value 0x40...

Page 189: ...Reserved 0xAC RT Event log size mask RW 0xfffffffc 0xB0 RT Event log position RW 0x00000000 0xB4 RT Event log interrupt position R 0x00000000 0xB8 0xBF Reserved Reset value is affected by the external...

Page 190: ...rw rw r rw rw rw 17 BM Timer overflow interrupt enable BMTOE 16 BM DMA error interrupt enable BMDE 10 RT Table access error interrupt enable RTTEE 9 RT DMA error interrupt enable RTDE 8 RT Transfer tr...

Page 191: ...0 Stopped 01 Executing command 10 Waiting for time slot 7 3 Schedule address low bits SCADL Bit 8 4 of currently executing if SCST 001 or next schedule descrip tor address 2 0 Schedule state SCST 000...

Page 192: ...address If running this will cause a jump after the current transfer has finished 31 24 23 0 RESERVED SCHEDULE TIME SCTM 0 0 r r 23 0 Elapsed transfer list time in microseconds read only Set to zero w...

Page 193: ...3 4 3 Note This register is an optional feature see BC Status and Config Register bit 28 31 0 BC TRANSFER SLOT POINTER 0 r 31 0 Points to the transfer descriptor corresponding to the current time slot...

Page 194: ...us reset signal enable BRS Set to 1 to pulse the busreset output when a reset remote terminal mode code has been received 6 Reads 1 if current address was set through external inputs After setting the...

Page 195: ...ct 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESERVED RRTB RRT ITFB ITF ISTB IST DBC 0 0 0 0 0 0 0 0 r rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TBW TVW TSB TS SDB SD SB S 0 0 1...

Page 196: ...RT s time tag counter in microseconds minus 1 15 0 Time tag value TVAL Current value of running time tag counter 31 21 20 2 1 0 RESERVED EVENT LOG SIZE MASK RES 0xFFFFFFC r rw r 31 0 Mask determining...

Page 197: ...from buffer end to buffer start 4 External sync start EXST If set to 1 BMEN will be set to 1 and the BM is started when an external BC sync pulse is received 3 Invalid mode code log IMCL Set to 1 to l...

Page 198: ...C 15 Transmit status word TSW 14 Reset remote terminal broadcast RRTB 13 Reset remote terminal RRT 12 Inhibit override inhibit terminal flag bit broadcast ITFB 11 Inhibit override inhibit terminal fla...

Page 199: ...x00000000 r rw r 31 0 Pointer to the next position that will be written to in the BM log buffer Only bits 21 3 are settable i e the buffer can not cross a 4 MB boundary Bits 31 22 read the same as the...

Page 200: ...sed by the ADC and the DAC can be used for general purpose input out put providing 0 8 16 or 24 channels The ADC interface supports 8 and 16 bit data widths It provides chip select read convert and re...

Page 201: ...BAAPB slave interface The ADC interface is intended for amongst others the following devices Name Width Type AD574 12 bit R C CE CS RDY tri state AD674 12 bit R C CE CS RDY tri state AD774 12 bit R C...

Page 202: ...ports 8 and 16 bit wide input data The ADC interface provides an 8 bit address output shared with the DAC interface Note that the address timing is independent of the acquisition timing The ADC interf...

Page 203: ...till the Chip Select signal is asserted is programma ble in terms of system clock periods Note that the programming of Chip Select and Read Convert timing is implemented as a common parameter At the...

Page 204: ...sserted during the conversion The duration of the asserted period of the Write Strobe is programmable in terms of system clock periods At the end the conversion an interrupt is generated The status of...

Page 205: ...Polarity of ADC chip select 0b active low 1b active high 6 RDYMODE Mode of ADC ready 0b unused i e open loop 1b used with time out 5 RDYPOL Polarity of ADC ready 0b falling edge 1b rising edge 4 TRIGP...

Page 206: ...ble before ADO WR period ADO WR asserted period ADO Dout 15 0 stable after ADO WR period 24 3 2 Status Register ADSTAT R Table 225 Status register 6 DACNO DAC conversion request rejected due to ongoin...

Page 207: ...te access to the register initiates a digital to analogue conversion provided that no other DAC or ADC conversion is ongoing otherwise the request is rejected Note that only the part of ADO Dout 15 0...

Page 208: ...ster ADDOUT R Table 232 Data Output Register W 15 0 DOUT Output data ADO Dout 15 0 All bits are cleared to 0 at reset Note that only the part of ADO Dout 15 0 neither used by the DAC nor the ADC can b...

Page 209: ...N units Software must enable clock and release reset described in section 26 before GRCAN configuration and transmission can start External IO selection per GRCAN unit is made in the system IO configu...

Page 210: ...ransmitted the DMA controller issues an interrupt After the reception has been set up via the AMBA APB interface messages are received by the CAN core To store messages to memory the DMA controller in...

Page 211: ...eive input i e 0 and 1 The active pair i e 0 or 1 is selectable by means of a configuration register bit Note that all recep tion and transmission is made over the active pair For each pair there is o...

Page 212: ...the 4 least significant byte address bits are zero for the first word in a CAN message The size of the buffer is defined by the CanTxSIZE SIZE field specifying the number of CAN mes sages 4 that fit i...

Page 213: ...uffer a prefetch of this CAN message from the circular buffer to a local prefetch buffer in the CAN controller will be performed The CAN controller can thus hold two CAN messages for transmission one...

Page 214: ...read pointer can be used to determine which message caused the AHB error Note that it could be any of the four word accesses required to read a message that caused the AHB error If the CanCONF ABORT b...

Page 215: ...Off Bus off condition Pass Error passive condition The Tx TxEmpty and TxIrq interrupts are only generated as the result of a successful message trans mission after the CanTxRD READ pointer has been i...

Page 216: ...d which applies to the error counter buss off condition and error passive condition 25 6 3 Location The location of the circular buffer is defined by a base address CanRxADDR ADDR which is an absolute...

Page 217: ...d after an AMBA AHB error occurs as indicated by the CanSTAT AHBErr bit being 1b The accesses will be disabled until the CanSTAT register is read and automatically clearing bit CanSTAT AHBErr 25 6 7 E...

Page 218: ...e CAN core is according to the CAN standard which applies to the error counter buss off condition and error passive condition 25 7 Global reset and enable When the CanCTRL RESET bit is set to 1b a res...

Page 219: ...01C SYNC Code Filter Register 0x100 Pending Interrupt Masked Status Register 0x104 Pending Interrupt Masked Register 0x108 Pending Interrupt Status Register 0x10C Pending Interrupt Register 0x110 Inte...

Page 220: ...the node delay Note that for minimizing the node delay then set either SCALER 0 or BRP 0 Note that the resulting bit rate is system clock SCALER 1 BPR 1 PS1 1 PS2 where PS1 is in the range 1 to 15 an...

Page 221: ...MBA AHB error occurs while the Can CONF ABORT bit is set to 1b 25 8 3 Control Register CanCTRL R W Table 237 Control Register 1 RESET Reset complete core when 1 0 ENABLE Enable CAN controller when 1 R...

Page 222: ...is 1b the channel is disabled i e the ENABLE bit is cleared to 0b if the arbitration on the CAN bus is lost Note that in the case an AHB bus error occurs during an access while fetching transmit data...

Page 223: ...e to fill the buffer There is always one message position in buffer unused Software is responsible for not over writing the buffer on wrap around i e setting WRITE READ The field is implemented as rel...

Page 224: ...eceive Channel Control Register CanRxCTRL R W Table 246 Receive Channel Control Register 1 ONGOINGReception ongoing read only 0 ENABLE Enable channel All bits are cleared to 0 at reset Note that in th...

Page 225: ...ss of a transfer Note that the WRITE field can be written to in order to set up the starting point of a transfer This should only be done while the receive channel is not enabled 25 8 16 Receive Chann...

Page 226: ...and read interrupt status When an interrupt occurs the corresponding bit in the Pending Interrupt Register is set The normal sequence to initialize and handle a module interrupt is Set up the softwar...

Page 227: ...nterrupt Mask Register CanIMR R W Pending Interrupt Clear Register CanPICR W 16 TxLoss Message arbitration lost during transmission could be caused by communications error as indicated by other interr...

Page 228: ...tifier Extension 1b for Extended Format 0b for Standard Format RTR Remote Transmission Request 1b for Remote Frame 0b for Data Frame bID Base Identifier eID Extended Identifier DLC Data Length Code ac...

Page 229: ...RS illegal TxErrCntr Transmission Error Counter RxErrCntr Reception Error Counter AHBErr AHB interface blocked due to AHB Error when 1b OR Reception Over run when 1b OFF Bus Off mode when 1b PASS Erro...

Page 230: ...registers The clock enable register defines if a clock is enabled or disabled A 1 in a bit location will enable the corresponding clock while a 0 will disable the clock The core reset register allows...

Page 231: ...The proces sor core will be automatically gated off when it enters power down mode The FPU will be gated off when the LEON3FT processor core connected to the FPU have floating point disabled or when...

Page 232: ...4 3 2 1 0 R NV SP TD AS MP AU L3 ID R H5 U4 U3 U2 U1 U0 P1 P0 DA IS1 IS0 IM1 IM0 S1 S0 M1 M0 MC PX PR IA SA 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r rw rw rw rw rw rw rw rw r...

Page 233: ...3 ID R H5 U4 U3 U2 U1 U0 P1 P0 DA IS1 IS0 IM1 IM0 S1 S0 M1 M0 MC PX PR IA SA 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r r rw rw rw rw rw rw rw r rw rw rw rw rw rw rw rw rw rw rw...

Page 234: ...k A reset will be gen erated as long as the corresponding bit is set to 1 The bits in clock enable and core reset registers can only be written when the corresponding bit in the unlock register is 1 I...

Page 235: ...com gaisler GR716 27 3 Registers The core s registers are mapped into APB address space Table 261 Clock gate unit registers APB address offset Register 0x00 Unlock register 1 0x04 Clock enable registe...

Page 236: ...2 1 0 RESERVED S1 S0 A7 A6 A5 A4 A3 A2 A1 A0 D3 D2 D1 D0 SP C1 C0 ML D3 D2 D1 D0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 31 22...

Page 237: ...17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED S1 S0 A7 A6 A5 A4 A3 A2 A1 A0 D3 D2 D1 D0 SP C1 C0 ML D3 D2 D1 D0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r rw rw rw rw rw rw rw rw rw rw rw...

Page 238: ...res Each DMA core provides a flexible direct memory access controller The core can perform burst transfers of data between AHB and APB peripherals at aligned or unaligned memory addresses One DMA chan...

Page 239: ...at are named RESERVED RES or R are read only fields These fields can be written with zero or with the value read from the same register field 28 2 3 Descriptor type 0 Each descriptor consists of a fou...

Page 240: ...the next descriptor in the M2B descriptor chain or NULL 3 1 M2B descriptor version This bitfield should be set to 0 in normal mode and set to 1 for extended mode 0 M2B descriptor type DT Descriptor t...

Page 241: ...ess offset 0x0C 31 3 2 1 0 RESERVED E S C 2 M2B descriptor error E If set to one an error was generated during execution of the M2B descrip tor See error register for more information 1 M2B descriptor...

Page 242: ...M descriptor size SIZE Size in Bytes of the data that will be written to the address specified in the B2M address register 5 B2M descriptor Fixed Start address FS If set to 1 in extended mode the star...

Page 243: ...onditional descriptor the DT bit field in the descriptor s control field needs to be set to 0 Bits 31 0 of the conditional address triggering line field will point to the address that the DMA core wil...

Page 244: ...conditional termination expression matches to true 15 4 Conditional descriptor counter reset value COUNTER_RST Reset value of the conditional counter timer that is executed before every polling or tri...

Page 245: ...ore going back to executing the conditional trigger ing An optional retry counter COND_RETRIES can be enabled to set the maximum number of retries that are allowed before conditional condition is cons...

Page 246: ...e NULL 3 1 Conditional descriptor version This bit field should be set to 0 in normal mode and set to 1 for extended mode 0 Conditional descriptor type DT Descriptor type field 0 for data descriptors...

Page 247: ...Conditional Mask COND_MASK Bit mask used in the conditional descriptor termination condi tion matching Table 290 GRDMAC Conditional descriptor data field for version 1 address offset 0x10 31 0 DATA_MA...

Page 248: ...re will fetch a new descriptor after the successful completion of the previous one following the pointers in the linked list When the core reaches a NULL pointer in the M2B chain it will switch to the...

Page 249: ...d at an error or when manually disabled by user or software After the descriptors pair has been fetched the conditional execution will follow these steps a the core will execute the conditional counte...

Page 250: ...ng settings The Interrupt on Error Enable bit IEE in the control register provides a way to generate interrupts in the event of errors Error generation is discussed further in the next paragraph An in...

Page 251: ...lso read directly from the channel error field CHERR of the error register Additionally an interrupt will be generated if the Interrupt on Error Enable bit IEE and the global Interrupt Enable IE bit i...

Page 252: ...tus register 0x08 Interrupt mask register 0x0C Error register 0x10 Channel Vector Pointer 0x14 Timer Reset Value Error Register 0x18 Capability register 0x1C Interrupt flag register 0x20 Reserved 0x24...

Page 253: ...riptor execution 4 Simplified mode SM Set to one to use the core in simplified mode of operation 3 Interrupt enable for Errors IEE Set to one to enable interrupt generation on error Interrupt gener at...

Page 254: ...error was of type conditional execution error This field is cleared by writing a one to it 3 Transfer Error TE One if the last generated error was of type transfer error This field is cleared by writ...

Page 255: ...6 10 9 Not used 8 Second AHB Master H1 If set to one the second AHB master interface AHBM1 is enabled 7 4 Channel Number NCH The maximum number of supported DMA channels in the core is 15 1 3 0 Versio...

Page 256: ...ll read data from 31 16 15 3 2 1 0 SIZE RESERVED IE R EN NR 0 NR 0 NR rw r rw r rw 31 16 M2B descriptor size SIZE Size in Bytes of the data that will be fetched from the address specified in the M2B a...

Page 257: ...pped at 0xCCC00104 and will use the mask 0x00000100 for the termination condition This mask will be ANDed with the status regis 31 0 ADDR NR rw 31 0 B2M Address ADDR Starting address the core will wri...

Page 258: ...xample we extend the previous example in chapter 12 2 3 by using the DMA to transfer 8 samples from the ADC to the local memory before interrupting the processor The DMA can be pro grammed to transfer...

Page 259: ...iptor 0 next descriptor pointer lsb set to 1 for cond desc 0x01004 0x0000001C M2B conditional descriptor 0 address ADC0 Interrupt register address 0x01008 0x00040013 M2B conditional descriptor 0 contr...

Page 260: ...er 0x80200000 0x001004D GRDMAC Control register Enable channel in extended mode 0x80050018 0x00000009 ADC0 Mask register Enable events from ADC0 0x8005000C 0x00000800 ADC0 Select trigger counter 2 in...

Page 261: ...reset described in section 26 before General Purpose I O port GRGPIO configuration and transmission can start External IO selection per General Purpose I O port GRGPIO unit is made in the system IO c...

Page 262: ...ith programmable output enable The input from each buffer is synchronized by two flip flops in series to remove potential meta stability The synchronized values can be read out from the I O port data...

Page 263: ...complete if enabled in mask register Note that SEQCNT can be set to infinite and sequencer will need to be disabled manually 29 4 2 Cascade mode Multiple sequencer memories can combined in order to ge...

Page 264: ...vent and start when event is detected on the input The sampler can be enabled manually or by any of the interrupt requests on the APB bus Samples will be stored in the SAMPSEQ and interrupts can be op...

Page 265: ...k register logical OR 0x60 Input enable register logical AND 0x64 I O port output register logical AND 0x68 I O port direction register logical AND 0x6C Interrupt mask register logical AND 0x70 Input...

Page 266: ...c utive writes would make the first write to the set clear register invalid and the Set Clear will not take place It is recommended to use the SPARC feature double store and the addresses for the Set...

Page 267: ...0x0C IMASK Interrupt mask register Interrupt Mask Register 29 6 5 Table 317 0x10 IPOL Interrupt polarity register Interrupt Polarity Register 31 0 DATA r 31 0 I O port input value DATA Data value read...

Page 268: ...12 8 IRQGEN Software can dynamically configure each I O to drive either of the 4 interrupt lines asso ciated with each GPIO unit cf section 2 12 4 0 NLINES Number of pins in GPIO port 1 31 29 28 24 2...

Page 269: ...effect 31 0 IPEN 0 rw 31 0 IPEN If IPEN n is set to 1 then values from GPIO line n will be visible in the data register Oth erwise the GPIO line input is gated off to disable input signal propagation...

Page 270: ...Set Clear registers will update the corresponding register according to New value Old value OR First write OR Old value AND NOT Second write The first write is used to set bits and second write is us...

Page 271: ...cycle delay between each repetition By setting this register to 0 creates con tiguous sequences 20 13 SEQCNT Set the number of times to repeat the loop for GPIO output pin n The sequence will be loope...

Page 272: ...cally set high when the inter rupt request defined in INT occurs This bit is cleaned automatically when such event happens 19 14 INT number of the interrupt request enabling the pulse sampler 13 1 Res...

Page 273: ...ry register Sequence Memory Register 29 6 19 Table 331 0x110 n 0x20 SAMPSEQ Sampling Sequence memory register Sampling Sequence Memory Register n 31 0 VALUE 0x00000000 rw 31 0 GPIO output pin sequence...

Page 274: ...1 0 Reserved ST SF SE 0x00000000 0 0 0 r wc wc wc 31 3 Reserved 2 Sampler trigger detected ST 1 Sampler FIFO full SF 0 Sequence ended SE 31 3 2 1 0 Reserved ST SF SE 0x00000000 0 0 0 r wc wc wc 31 3...

Page 275: ...able indi vidual PWM units The unit GRCLKGATE can also be used to perform reset of individual PWM units Software must enable clock and release reset described in section 26 before PWM configuration an...

Page 276: ...amount of time at the end of the period and stays active in between The two inactive time periods are normally but not necessarily equally long For the core to generate a PWM independent of whether a...

Page 277: ...between when one of the PWM signals of a PWM pair goes inactive and when the other signal goes active This delay is called dead band time By default the core does not generate any dead band time but...

Page 278: ...he bits in the Interrupt pending register stay set until software clears them by writing 1 to them When an interrupt is generated or when the interrupt scaler counter is increased an output tick is ge...

Page 279: ...can be used by software if it wants to change more than one of the values and it is required that all values change in the same PWM period It can also be used to synchronize the use of new values for...

Page 280: ...bits 1 for the PWM s dead band time counters Read only 15 13 Reports number of implemented scalers 1 Read only 12 8 Reports number of bits for the scalers 1 Read only 7 3 Reports number of bits for t...

Page 281: ...The dead band time has passed once the dead band counter reach the value of this field When this register is written the actual compare value used inside the core is not updated immediately instead a...

Page 282: ...c PWM is generated Reset value is 0b0 7 When this pair_zero bit is set to 0b1 and the pair bit is set to 0b0 the complement output is always set to zero When this bit is set to 0b0 and the pair bit is...

Page 283: ...e by means of control registers 31 2 PacketWire interface A PacketWire link comprises four ports for transmitting the message delimiter the bit clock the serial bit data and an abort signal A link als...

Page 284: ...ress field of the descriptor should point to the start of where the received data is to be stored The address need not be word aligned If the interrupt enable IE bit is set an interrupt will be genera...

Page 285: ...in the descriptor pointer register The address must be aligned to a 16 kByte boundary Bits 31 to 14 hold the base address of descriptor area while bits 13 to 4 form a pointer to an individual descrip...

Page 286: ...A AHB error was encountered either when reading a descriptor or when writing data Any active reception was aborted and the DMA channel was disabled It is recommended that the receiver is reset after a...

Page 287: ...0 0 0 r r wc wc wc 31 4 RESERVED 3 Active ACTIVE DMA access ongoing 2 Receiver AMBA Error RA DMAAMBAAHB error cleared by writing a logical 1 1 Receiver Interrupt RI DMA interrupt cleared by writing a...

Page 288: ...RESERVED MODE 0 0 r r r rw 31 24 REVISION Revision number read only 23 8 FIFOSIZE FIFO size in bytes read only 23 1 RESERVED 0 MODE Enable framing mode when set else packet mode when cleared 31 20 19...

Page 289: ...ters 32 2 PacketWire interface A PacketWire link comprises four ports for transmitting the message delimiter the bit clock the serial bit data and an abort signal A link also comprises additional port...

Page 290: ...of the descriptor should point to the start of the data to be sent The address need not be word aligned If the interrupt enable IE bit is set an interrupt will be generated when the transfer has comp...

Page 291: ...able This bit should always be set when new descriptors are enabled even if transmission is already active The descriptors must always be enabled before the transmission enable bit is set 32 3 4 Descr...

Page 292: ...4 RESERVED 3 Active ACTIVE DMA access ongoing 2 Transmitter AMBA Error TA DMAAMBAAHB error cleared by writing a logical 1 1 Transmitter Interrupt TI DMA interrupt cleared by writing a logical 1 0 Tran...

Page 293: ...24 REVISION Revision number read only 23 8 FIFOSIZE FIFO size in bytes read only 7 0 RESERVED 31 20 19 8 7 6 5 4 3 2 0 HALFBAUD RESERVED BUSY POS READY POS VALID POS CLK RISE CLK MODE RESERVED 1 0 0 1...

Page 294: ...t External IO selection and configuration is made in the system IO and LVDS configuration registers GRGPREG in the address range from 0x8000D000 to 0x8000D03F and 0x80007030 See section 7 1 for furthe...

Page 295: ...s with a valid destination address in the first received byte Packets with address mismatch will be silently discarded except in promiscuous mode which is covered in section 33 6 10 The second byte is...

Page 296: ...n a NULL character has been received and the CTRL AS bit is set The state of the link interface determines which type of characters that are allowed to be transmitted which together with the requests...

Page 297: ...data valid signal The receiver and GRSPW2_PHY are located in a separate clock domain which runs on a clock outputed by the GRSPW2_PHY The receiver is activated as soon as the link interface leaves the...

Page 298: ...nk rate during initialization all states up to and including the connecting state The register is also used to calculate the link interface FSM timeouts 6 4 us and 12 8 us as defined in the SpaceWire...

Page 299: ...e bit is written the current time value TC TIMECNT field is incremented and a Time Code con sisting of the new time value together with the current control flags TC TCTRL field is sent The CTRL TI bit...

Page 300: ...code is received such that the corre sponding ISR bit is set to 1 If a matching interrupt acknowledge code is received the corresponding ISR timer is stopped If the ISR timer expires before an interr...

Page 301: ...gister is set to 1 The TICKOUT signal is asserted for one clock cycle as well and an AMBA interrupt is generated if the IE bit in the Control register and IQ bit in the Interrupt distribution control...

Page 302: ...e address register has a corresponding mask register Only bits at an index containing a zero in the corresponding mask register are compared This way a DMA channel can accept a range of addresses Ther...

Page 303: ...command No Yes No Set DMA channel number to 0 Process RMAP command Separate addressing No Yes dma n addr rxaddr dma n mask Channel enabled Increment channel number and pid 1 and defaddr defmask rxadd...

Page 304: ...ts own range If all channels use the default registers they will accept the same address range and the enabled channel with the lowest number will receive the packet Finally the descriptor table and C...

Page 305: ...l each time descriptors are enabled as mentioned above If the rxdescav bit is 0 and the nospill bit is 0 the packets will be discarded If nospill is 1 the core waits until rxdescav is set and the char...

Page 306: ...the header CRC was incorrect However the data should not be used when the header is corrupt and therefore the DC bit is unimportant in this case When the header is not corrupted the CRC value will al...

Page 307: ...ore for transmission Four steps need to be performed before transmissions can be done with the core First the link inter face must be enabled and started by writing the appropriate value to the ctrl r...

Page 308: ...ata field is zero 16 Append header CRC HC Append CRC calculated according to the RMAP specification after the data sent from the header pointer The CRC covers all bytes from this pointer except a numb...

Page 309: ...aborted the packet is truncated and an EEP is inserted This is only useful if the packet needs to be aborted because of congestion on the SpaceWire network If the congestion is on the AHB bus this wi...

Page 310: ...P is a protocol which is designed to provide remote access via a SpaceWire network to memory mapped resources on a SpaceWire node It has been assigned protocol ID 0x01 It provides three oper ations wr...

Page 311: ...eration performed for each RMAP verified write command the incrementing address bit can be set to any value Non verified writes have no restrictions when the incrementing bit is set to 1 If it is set...

Page 312: ...rol possibilities There is an enable bit in the control register of the core which can be used to completely disable the RMAP target When it is set to 0 no RMAP packets will be handled in hardware ins...

Page 313: ...te increment ing address Executed normally If length is not one of the allowed rmw val ues nothing is done and error code is set to 11 If the length was correct alignment restric tions are checked nex...

Page 314: ...is sent 0 1 1 1 0 1 Write incre menting address ver ify before writing no acknowledge Executed normally Length must be 4 or less Otherwise nothing is done Same alignment restric tions apply as for rm...

Page 315: ...onsecutive accesses HTRANS will always be NONSEQ in this case while for incrementing accesses it is set to SEQ after the first access This feature is included to support non incrementing reads and wri...

Page 316: ...an error response The data returned in a read access is zero while a write access has no effect Table 376 SpaceWire Plug and Play support SpW PnP Address Name Acronym Service Field set Field Access t...

Page 317: ...lug and Play Application Count PNPACNT Device Information Application Support Application Count read 0x00080000 SpaceWire Plug and Play Time Code Counter 1 PNPTCC SpaceWire Protocol Device Con figurat...

Page 318: ...logical address OLA Shows the value of the Initiator Logical Address field from the last successful compare and swap command that set the Device ID field 23 22 Owner address length OAL Shows how many...

Page 319: ...r up and when the link interface is not in run state Table 386 0x00000009 PNPUVEND SpaceWire Plug and Play Unit Vendor and Product ID 31 16 15 0 VEND PROD r r 31 16 Unit vendor ID VEND Shows the unit...

Page 320: ...L PNPA 2 Table 391 0x0000C000 PNPACNT SpaceWire Plug and Play Application Count 31 8 7 0 RESERVED AC 0x000000 0x00 r r 31 8 RESERVED 7 0 Application count AC Constant value of 0 indicating that no app...

Page 321: ...n address field i e it does not match the DEFADDR register Cleared when complete PNPLSTS is written with zero 0 RESERVED Table 394 0x00084009 PNPLCTRL SpaceWire Plug and Play Link Control 31 5 4 3 2 1...

Page 322: ...EF2 Bit field description 15 8 Example bit field 1 EF1 Bit field description 7 0 Example bit field 0 EF0 Bit field description Table 398 Reset value definitions Value Description 0 Reset value 0 Used...

Page 323: ...eceive extended 0xAC INTTO Interrupt timeout 0xB0 INTTOEXT Interrupt timeout extended 0xB4 TICKMASK Interrupt tick out mask 0xB8 TICKMASKEXT AUTO ACK Interrupt auto acknowledge mask Interrupt tick out...

Page 324: ...ated by CTRL PO bit Reserved bit in one port configurations Reset value is 1 if the boot strap signals are configured for SpaceWire RMAP enable see section 3 1 otherwise the reset value is 0 19 18 Spa...

Page 325: ...n state for the time code to be sent 3 Interrupt Enable IE If set AMBA interrupt generation is enabled for the events that are individu ally maskable by the CTRL TQ CTRL LI INTCTRL IQ INTCTRL AQ and I...

Page 326: ...er to the index number of the data and strobe signals 8 Early EOP EEP EE Set to one when a packet is received with an EOP after the first byte for a non rmap packet and after the second byte for an RM...

Page 327: ...taken from the CLKDIV10 input signal 31 8 7 0 RESERVED DESTKEY 0x000000 r rw 31 8 RESERVED 7 0 Destination key DESTKEY RMAP destination key 31 8 7 6 5 0 RESERVED TCTRL TIMECNT 0x000000 0x0 0x00 r rw...

Page 328: ...rrupt code is gen erated when a received packet on this DMA channel is truncated due to a maximum length violation Field is only present if interrupt distribution is supported which is indicated by th...

Page 329: ...scriptor is set as well This happens both if the packet is terminated by an EEP or EOP 2 Transmit interrupt TI If set an interrupt will be generated when a packet is transmitted if the interrupt enabl...

Page 330: ...4 Descriptor selector DESCSEL Offset into the descriptor table Shows which descriptor is cur rently used by the core For each new descriptor read the selector will increase with 16 and eventu ally wra...

Page 331: ...e bit was already set when the event occurrepriod 23 Interrupt code transmit on invalid address IA If set to 1 an interrupt code with the interrupt num ber specified in the INTNUM field is sent each t...

Page 332: ...is written to 1 the interrupt interrupt acknowledge code specified in the TXINT field will be sent The actual sending of the interrupt interrupt acknowledge code might be delayed depending on the valu...

Page 333: ...atching interrupt code was sent by software valid for interrupt acknowledge Note that the number of implemented bits depends on the number of sup ported interrupts INTCTRL NUMINT field When extended i...

Page 334: ...interrupts INTC TRL NUMINT field When extended interrupt mode is enabled this register is an extension of the Interrupt Tick out Mask register 31 26 25 20 19 14 13 8 7 4 3 2 1 0 INTNUM3 INTNUM2 INTNU...

Page 335: ...ber of implemented bits depends on the number of supported interrupts INTCTRL NUMINT field 31 0 ISR 0x00000000 wc 31 0 Interrupt distribution ISR ISR Each bit index holds the ISR bit value for the cor...

Page 336: ...an interrupt code and an interrupt acknowledge code and vice versa One global timer enable bit is used for all ISR bits If this bit is set to 1 the timer for each ISR bit is reloaded with the value in...

Page 337: ...2 31 16 15 0 VEND PROD r r Note Register is double mapped from SpaceWire Plug and Play address space into APB address space See section 33 10 for details 31 24 23 22 21 20 16 15 13 12 8 7 6 5 4 0 OLA...

Page 338: ...ote Register is double mapped from SpaceWire Plug and Play address space into APB address space See section 33 10 for details 31 16 15 0 VEND PROD rw rw Note Register is double mapped from SpaceWire P...

Page 339: ...s signaled by means of transferring a SpaceWire Time Code The transfer of the SpaceWire Time Code is synchronized with time maintained by the initiator To distinguish which SpaceWire Time Code is to b...

Page 340: ...or or a target but both have their respective time generator The Elapsed Time ET counter is implemented complying with the CUC T Field The number of bits representing coarse and fine time of a ET coun...

Page 341: ...Wire Time Codes The SpaceWire Time Codes are provided by this component and transmission of those codes to tar gets should be performed by a SpaceWire interface Transmission of CCSDS Time Codes throug...

Page 342: ...ter will send SpaceWire Time Code at every Second When the value is 0b00001 Space Wire Time Codes are sent at every 0 5 Seconds interval and so on maximum value of MAPPING can be 0b11111 but this valu...

Page 343: ...age in target will happen after the reception of qualifying SpaceWire Time Codes The qualifying SpaceWire Time Code is embedded in the Command Elapsed time part of time message sent from initiator Thi...

Page 344: ...sion and recep tion is time stamped current local time is stored in Time Stamp registers and interrupt transmitted is INTX and received interrupt is checked whether it received INRX If both distribute...

Page 345: ...4 Data formats All Elapsed Time ET information is compliant with the CCSDS Unsegmented Code defined in CCSDS and repeated hereafter 34 4 1 Numbering and naming conventions Convention according to the...

Page 346: ...C Command Elapsed Time 2 0x030 Command Elapsed Time 3 0x034 Command Elapsed Time 4 0x038 RESERVED 0x03C RESERVED 0x040 0x05F Datation Field 0x040 Datation Preamble Field 0x044 Datation Elapsed Time 0...

Page 347: ...ED 0x0C0 Interrupt Enable 0x0C4 Interrupt Status 0x0C8 Delay Count 0x0CC 0x0FF RESERVED 0x100 0x18F External Datation Field 0x100 External Datation 0 Mask 0x104 External Datation 1 Mask 0x108 External...

Page 348: ...e Value 0b00000 will send SpaceWire Time Codes every Second Value 0b00001 will send SpaceWire Time Codes every 0 5 Second Value 0b00010 will send SpaceWire Time Codes every 0 25 Second Value 0b00011 w...

Page 349: ...plemented registers are writable and readable 31 8 7 0 CV ETINC rw rw 31 8 CV Compensation Value Value added to FSINC for variations of drift of the target clock only for target Refer the spreadsheet...

Page 350: ...nterrupts at all SpaceWire Time Codes irrespective of any values in TSTC register Value all ones will send Distributed interrupts at complete match of SpaceWire Time Code with TSTC register only for i...

Page 351: ...conditions matched for external datation this bit will go high This bit will go low when all the implemented time values are read 23 RESERVED 22 16 FW Fine width of command CCSDS Time Code received Ca...

Page 352: ...iator the SpaceWire Time Codes generated internally using the local ET counter matches this register a Time Message TM interrupt will be generated which is used to send Time message over the SpaceWire...

Page 353: ...tion Preamble Field 31 0 CET2 0 rw 31 0 CET2 Command Elapsed Time 2 Initialize or Synchronise local ET counter value 64 to 95 31 0 CET3 0 rw 31 0 CET3 Command Elapsed Time 3 Initialize or Synchronise...

Page 354: ...34 6 17 Table 457 0x050 DET3 Datation Elapsed Time 3 Datation Elapsed Time 3 31 0 DET0 0 r 31 0 DET0 Datation Elapsed Time 0 CCSDS Time Code value 0 to 31 of local ET counter value 31 0 DET1 0 r 31 0...

Page 355: ...psed Time 2 Rx Time Stamp Elapsed Time 2 Rx 31 24 23 0 DET4 RESERVED 0 0 r r 31 24 DET4 Datation Elapsed Time 4 CCSDS Time Code value 128 to 135 of local ET counter value 23 0 RESERVED 31 16 15 0 RESE...

Page 356: ...value 96 to 127 when distributed interrupt received 31 24 23 0 TR4 RESERVED 0 0 r r 31 24 TR4 Time stamped local ET value 128 to 135 when distributed interrupt received 23 0 RESERVED 31 24 23 16 15 0...

Page 357: ...ble Field Latency Preamble Field 31 0 TT1 0 r 31 0 TT1 Time stamped local ET value 32 to 63 when distributed interrupt transmitted 31 0 TT2 0 r 31 0 TT2 Time stamped local ET value 64 to 95 when distr...

Page 358: ...ncy Elapsed Time 3 34 6 36 Table 476 0x0B4 LE4 Latency Elapsed Time 4 Latency Elapsed Time 4 31 0 LE0 0 rw 31 0 LE0 Latency Value 0 to 31 written by initiator only for target 31 0 LE1 0 rw 31 0 LE1 La...

Page 359: ...for target 31 10 9 8 7 6 5 4 3 2 1 0 RESERVED EDI3 EDI2 EDI1 EDI0 DIT DIR TT TM TR S 0 0 0 0 0 0 0 0 0 0 0 r wc wc wc wc wc wc wc wc wc wc 31 10 RESERVED 9 EDI3 Generated when conditions for External...

Page 360: ...The delay introduced is the value in this register multiplied by the system clock only for initiator 31 0 EDM0 0 rw 31 0 EDM0 External datation can be enabled by writing 1 into the bit for that corre...

Page 361: ...d External Datation 3 Mask registers are exactly same as External Datation 0 Mask Register The Definition of External Datation 1 Time External Datation 2 Time and External Datation 3 Time registers ar...

Page 362: ...upt will be raised when any of the timers with interrupt enable bit underflows The timer unit will signal an interrupt on appropriate line when a timer underflows if the interrupt enable bit for the c...

Page 363: ...itialized except for the WDOGDIS and WDOGNMI fields that are reset to 0 35 2 1 Window watchdog The watchdog has an optional lower boundary for reloading the watchdog timer Application can optionally s...

Page 364: ...reload value register 0x80003028 Timer 2 control register 0x8000302C Timer 2 latch register 0x80003030 Timer 3 counter value register 0x80003034 Timer 3 reload value register 0x80003038 Timer 3 contro...

Page 365: ...lue Register 31 16 16 1 0 RESERVED SCALER 0 all 1 r rw 16 1 0 Scaler value This value will also be set by writes to the Scaler reload value register Any unused most significant bits are reserved Alway...

Page 366: ...ed not to reload the timer values until set again 11 Enable latching EL If set on the next matching interrupt the latches will be loaded with the corre sponding timer values The bit is then automatica...

Page 367: ...Disable Watchdog Output WS WDOGDIS If this field is set to 1 then the GPTO WDOG and GPTO WDOGN outputs are disabled fixed to 0 and 1 respectively This functionality is only available for the last tim...

Page 368: ...r underflows if the interrupt enable bit for the current timer is set The interrupt pending bit in the control register of the underflown timer will be set and remain set until cleared by writing 1 To...

Page 369: ...reload value register 0x80004028 Timer 2 control register 0x8000402C Timer 2 latch register 0x80004030 Timer 3 counter value register 0x80004034 Timer 3 reload value register 0x80004038 Timer 3 contro...

Page 370: ...lue Register 31 16 16 1 0 RESERVED SCALER 0 all 1 r rw 16 1 0 Scaler value This value will also be set by writes to the Scaler reload value register Any unused most significant bits are reserved Alway...

Page 371: ...ed not to reload the timer values until set again 11 Enable latching EL If set on the next matching interrupt the latches will be loaded with the corre sponding timer values The bit is then automatica...

Page 372: ...DH CH IP IE LD RS EN 0 0 0 0 0 0 r r rw wc wc rw rw rw 31 7 Reserved Always reads as 000 0 6 Debug Halt DH Value of GPTI DHALT signal which is used to freeze counters e g when a sys tem is in debug m...

Page 373: ...system IO configuration registers GRG PREG in the address range from 0x8000D000 to 0x8000D03F See section 7 1 for further informa tion The system can be configured to protect and restrict access to t...

Page 374: ...ndi tion is defined in the I2C bus specification and is dependent on the bus bit rate Figure 58 shows a data transfer taking place over the I2C bus The master first generates a START condition and the...

Page 375: ...k cycles toggles and keeps the new level for two system clock cycles The synchronizers and filters constrain the minimum system frequency The core requires the SCL signal to be stable for at least fou...

Page 376: ...he address The access size byte halfword or word used on AHB is set via the HSIZE field in the I2C2AHB config uration register The core always respects the access size specified via the HSIZE field If...

Page 377: ...ched When clock stretching is disabled NACK field is 1 the core will never stretch the SCL line If the core is busy performing DMA when it is addressed the address will not be acknowledged If the core...

Page 378: ...med through registers mapped into APB address space Table 506 I2 C slave registers APB address offset Register 0x00 Control register 0x04 Status register 0x08 Protection address register 0x0C Protecti...

Page 379: ...I2C accesses Otherwise the core will not react to I2C traffic 31 3 2 1 0 RESERVED PROT WR DMA 0x0 0 0 0 r wc r wc 31 3 RESERVED 2 Protection triggered PROT Full access is granted the I2C2AHB interface...

Page 380: ...slave configuration address register I2C Slave Configuration Address Register 31 7 6 0 RESERVED I2CSLVADDR 0 0x50 r rw 31 7 RESERVED 6 0 I2C slave memory address I2CSLVADDR Address that slave respond...

Page 381: ...system IO configuration register GRG PREG in the address range from 0x8000D000 to 0x8000D03F See section 7 1 for further informa tion Each I2CMSTx unit controls its own external pins and has a unique...

Page 382: ...gure 61 shows a data transfer taking place over the I2C bus The master first generates a START condition and then transmits the 7 bit slave address The bit following the slave address is the R W bit w...

Page 383: ...not allow the implementation fulfill the 100 ns minimum requirement for data setup time required for Fast mode operation For compatibility with the I2 C Specification in terms of minimum required dat...

Page 384: ...nt bit of the transmit register R W is set to 0 2 Generate START condition and send contents of transmit register by setting the STA and WR bits in the command register 3 Wait for interrupt or for TIP...

Page 385: ...slave to the transmit register 6 Set the WR bit in the command register 7 Wait for interrupt or for TIP bit in the status register to go low 8 Read RxACK bit in the status register RxACK should be lo...

Page 386: ...s set to 0 The minimum recommended value of this reg ister is 0x0003 Lower values may cause the master to violate I2 C timing requirements due to syn chronization issues 31 8 7 6 5 0 RESERVED EN IEN R...

Page 387: ...ledge RxACK Received acknowledge from slave 1 when no acknowledge is received 0 when slave has acked the transfer 6 I2 C bus busy BUSY This bit is set to 1 when a start signal is detected and reset to...

Page 388: ...See section 7 1 for further information Each I2CSLVx unit controls its own external pins and has a unique AMBA address described in chapter 2 11 I2CSLV unit 0 and 1 has identical configuration and sta...

Page 389: ...ace over the I2C bus The master first generates a START condition and then transmits the 7 bit slave address I2C also supports 10 bit addresses which are dis cussed briefly below The bit following the...

Page 390: ...tected if the SDA line while SCL is high is at one value for two system clock cycles toggles and keeps the new level for two system clock cycles The synchronizers and filters constrain the minimum sys...

Page 391: ...eration the core will respond to all subsequent requests with the byte located in the Transmit Register If TMOD is 1 the core will drive SCL low after a master has acknowledged the transmitted byte SC...

Page 392: ...egister 3 Transmit Mode TMOD Selects how the core handles reads 0 The slave transmits the same byte to all if the master requests more than one byte in the transfer The slave then NAKs all read reques...

Page 393: ...read or write request This bit does not get set to 1 when the core responds with a NAK to an address that does not match the cores address This bit is cleared by writing 1 to this position writes of 0...

Page 394: ...www cobham com gaisler GR716 39 3 6 Table 527 0x14 TX Transmit register Transmit Register 31 8 8 7 0 RESERVED TRABYTE 0 NR r rw 31 8 RESERVED 7 0 Transmit Byte TRABYTE Byte to transmit on the next mas...

Page 395: ...or more information 40 1 Overview The LEON3FT microcontroller implements an interrupt scheme where interrupt lines are routed together with the remaining AHB APB bus signals forming an interrupt bus T...

Page 396: ...one of two levels 0 or 1 as programmed in the interrupt level register Level 1 has higher priority than level 0 The interrupts are prioritised within each level with interrupt 15 having the highest pr...

Page 397: ...Where the bus interrupt line X is remapped to controller extended interrupt number 16 32 then corresponding bit in the range 16 32 and bit 1 of the pending register will be set when a peripheral asser...

Page 398: ...g interrupt handling The interrupt controller listens to the system interrupt vector when reacting to interrupt line assertions This means that the Interrupt Assertion Timestamp Register s will not be...

Page 399: ...ocessors for error mode and to allow forcing a specific processor into error mode This can be used to monitor and re boot processors without reset ing the system 40 2 8 Restart processor from internal...

Page 400: ...2100 Interrupt timestamp 0 counter register 0x80002104 Interrupt timestamp 0 control register 0x80002108 Interrupt assertion timestamp 0 register 0x8000210C Interrupt acknowledge timestamp 0 register...

Page 401: ...Clear Register 31 16 15 1 0 RESERVED IL 15 1 R 0 NR 0 r rw r 31 16 Reserved 15 1 Interrupt Level n IL n Interrupt level for interrupt n 0 Reserved 31 16 15 1 0 EIP 31 16 IP 15 1 R 0 0 0 rw rw r 31 16...

Page 402: ...operation of register shows the error mode of the LEON3FT pro cessor 1 error mode 0 debug run power down Write to register will force LEON3FT proces sor into error mode 31 27 26 20 19 16 15 0 NWDOG Re...

Page 403: ...0 wc r rw r 31 17 Interrupt Force Clear n IFC n Interrupt force clear for interrupt n 16 Reserved 15 1 Interrupt Force n IF n Force interrupt nr n 0 Reserved 31 6 5 0 RESERVED EID 5 0 0 0 r r 31 6 Res...

Page 404: ...002120 TCNT2 Interrupt Timestamp 2 Counter register 31 0 TCNT 0 r 31 0 Timestamp Counter TCNT Current value of timestamp counter The counter increments when ever a TSISEL field in a Timestamp Control...

Page 405: ...reby also stamp the next acknowledge of the inter rupt 4 0 Timestamp Interrupt Select TSISEL This field selects the interrupt number 1 31 to timestamp Table 544 0x80002114 ITSTMPC1 Timestamp 1 Control...

Page 406: ...he next acknowledge of the inter rupt 4 0 Timestamp Interrupt Select TSISEL This field selects the interrupt number 1 31 to timestamp Table 546 0x80002104 ITSTMPC3 Timestamp 3 Control Register 31 27 2...

Page 407: ...TASSERTION The current Timestamp Counter value is saved in this register when timestamping is enabled and the interrupt line selected by TSISEL is asserted Table 549 0x80002128 ITSTMPAS2 Interrupt As...

Page 408: ...ng is enabled the Acknowledge Stamped S2 field is 0 and the interrupt selected by TSISEL is acknowledged by a processor connected to the interrupt controller Table 553 0x8000212C ITSTMPAS2 Interrupt A...

Page 409: ...upt line n 4 1 Interrupt bus map n ID n 4 2 Map register for bus interrupt line n 4 2 Interrupt bus map n ID n 4 3 Map register for bus interrupt line n 4 3 31 3 2 1 0 BOOTADDR 31 3 RES AS w w 31 3 En...

Page 410: ...AP2 ID8 8 8 GRPWM ID9 9 9 GPTIMER0 ID10 10 10 GPTIMER0 ID11 11 11 GPTIMER0 0x8000230C IRQMAP3 ID12 12 12 GPTIMER0 ID13 13 13 GPTIMER0 ID14 14 14 GPTIMER0 ID15 15 15 GPTIMER0 0x80002310 IRQMAP4 ID16 16...

Page 411: ...2C IRQMAP11 ID44 5 44 APBUART4 ID45 6 45 APBUART5 ID46 7 46 APBUART6 ID47 8 47 I2CSLV1 I2C2AHB 0x80002330 IRQMAP12 ID48 11 48 SPICTRL ID49 12 49 SPICTRL ID50 13 50 I2CM ID51 14 51 I2CM 0x80002334 IRQM...

Page 412: ...e 0x17 AHB utilization per AHB master 0x18 AHB utilization total master CPU selection is ignored 0x22 Integer branches 0x28 CALL instructions 0x30 Regular type 2 instructions 0x38 LOAD and STORE instr...

Page 413: ...0x76 AHB byte accesses Filtered on CPU AHBM if SU 1 1 0x77 AHB half word accesses Filtered on CPU AHBM if SU 1 1 0x78 AHB word accesses Filtered on CPU AHBM if SU 1 1 0x79 AHB double word accesses Fil...

Page 414: ...by PWRX core 0x88 Request by PWTX core 0x89 Request by DMA core 0 0x8A Request by DMA core 1 0x90 0x9F Active when master selected by CPU AHBM field has request asserted while grant is deas serted for...

Page 415: ...termines the level where the counter keeps running when the CD field below has been set to 1 If this field is 0 the counter will count the time between event assertions If this field is 1 the counter...

Page 416: ...displayed by this register will be the maximum counter value reached with the settings in the counter s control register If the counter control register field CD is 0 then the value displayed by this...

Page 417: ...for configuration and status The AHB Memory Scrubber and Status Register unit MEMSCRUB unit is located on AHB bus in the address range from 0xFFF00000 to 0xFFF00FFF See units connections in the next...

Page 418: ...l an un correctable error as an AMBA error response so that it can be detected by the processor as described above 42 2 2 Correctable errors Not only error responses on the AHB bus can be detected Man...

Page 419: ...re can be set up to interrupt when the counters exceed given thresholds When this happens the NE bit plus one of the SEC SBC bits is set in the status register 42 2 5 External start and clear If the E...

Page 420: ...asing the start address as this can be done on the fly 42 2 10 Dual range support The scrubber can work over two non overlapping memory ranges This feature is enabled by writing the start end addresse...

Page 421: ...ck error counter threshold exceeded Asserted together with NE 9 CE Correctable Error Set if the detected error was caused by a correctable error and zero otherwise 8 NE New Error Deasserted at start u...

Page 422: ...completed Needs to be cleared by writing zero before a new task completed interrupt can occur 12 5 RESERVED 4 1 Burst length in 2 log of AHB bus cycles 0000 1 0001 2 0010 4 0011 8 0 Current state 0 I...

Page 423: ...572 0x20 POS Scrubber position register Scrubber Position Register 31 0 SCRUBBER RANGE HIGH ADDRESS 0 rw 31 0 The highest address in the range to be scrubbed The address bits below the burst size ali...

Page 424: ...threshold value for current scrub run correctable error count 21 14 Interrupt threshold value for current scrub block correctable error count 13 2 RESERVED 1 RECTE Scrub run correctable error count th...

Page 425: ...IO configuration registers GRG PREG in the address range from 0x8000D000 to 0x8000D03F See section 7 1 for further informa tion The system can be configured to protect and restrict access to the SPI t...

Page 426: ...e bus has clock polarity 0 and if the idle state is high the clock polarity is 1 The combined values of clock polarity CPOL and clock phase CPHA determine the mode of the SPI bus Figure 71 shows one b...

Page 427: ...t first All AMBA accesses are done in big endian format The first byte sent to or from the slave is the most significant byte 43 4 2 SPI status control register accesses RDSR WRSR The RDSR and WRSR in...

Page 428: ...re will not mask any address bits Therefore it is important that the SPI master respects AMBA rules when performing half word and word accesses A half word access must be aligned on a two byte address...

Page 429: ...protaddr is 0xA0000000 and protmask is 0xF0000000 Since protmask only has ones in the most significant nibble the check above can only be triggered for these bits The address range of allowed accesse...

Page 430: ...r wc r wc 31 3 RESERVED 2 Protection triggered PROT Set to 1 if an access has triggered the memory protection This bit will remain set until cleared by writing 1 to this position Note that the other f...

Page 431: ...s ter GRGPREG in the address range from 0x8000D000 to 0x8000D03F and 0x80007030 See sec tion 7 1 for further information Each SPICTRLx unit controls its own external pins and has a unique AMBA address...

Page 432: ...a transmission on the SPI bus data is either changed or read at a transition of SCK If data has been read at edge n data is changed at edge n 1 If data is read at the first transition of SCK the bus...

Page 433: ...es the MOSI line to transfer a word back to the slave The data line transitions depending on the clock polarity and clock phase in the same manner as in SPI mode The aforementioned slave delay of the...

Page 434: ...in SPI mode when SPISEL goes low the core configures MISO as an output and drives the value of the first bit scheduled for transfer If the core is configured into 3 wire mode the core will first list...

Page 435: ...on SPISEL even if the core is operating in loop mode and that the core can be configured to ignore SPISEL by setting the IGSEL field in the Mode register 44 3 Registers The core is programmed through...

Page 436: ...FACT OD CG ASELDEL TAC TTO IGSEL CITE R 0 0 0 0 0 0 0 0 0 0 rw rw rw rw rw rw rw rw rw rw r 31 Reserved 30 Loop mode LOOP When this bit is set and the core is enabled the core s transmitter and recei...

Page 437: ...CT If this bit is 1 the core s register interface is no longer compatible with the MPC83xx register interface The value of this bit affects how the PM field is utilized to scale the SPI clock See the...

Page 438: ...t is set to 1 the core will wait until it has set the SCK clock to its idle level see CI field before regarding a transfer as completed This setting only affects the behavior of the TIP status bit and...

Page 439: ...12 Overrun OV This bit gets set when the receive queue is full and the core receives new data The core continues communicating over the SPI bus but discards the new data This bit is cleared by writ in...

Page 440: ...l generate an interrupt when the UN bit in the Event register transitions from 0 to 1 10 Multiple master error enable MMEE When this bit is set the core will generate an interrupt when the MME bit in...

Page 441: ...r other lengths and REV 1 The data is placed with its LSB in bit 16 To illustrate this a transfer of a word with eight bits LEN 7 that are all set to one will have the following placement REV 0 0x0000...

Page 442: ...transmission can start External IO selection and configuration is made in the system IO and LVDS configuration registers GRGPREG in the address range from 0x8000D000 to 0x8000D03F and 0x80007030 See s...

Page 443: ...cts a slave through the slave s Slave Select CS signal and the clock line SCK transitions from its idle state Data is transferred from the master through the Master Output Slave Input MOSI signal and...

Page 444: ...er When appropriate commands are transferred by a master SPI device and EN bit in the SPI2 control register is enabled then the commands are processed by the SPI 2 protocol handler available in this c...

Page 445: ...the command word 1 and 2 the prefix and spare bits have fixed value in the current implementation these are reserved bits The spislave receives them and use it for validating the token If an invalid...

Page 446: ...he payload data section of the message a Payload CRC CRC 16 must be included at the end of the message The generator polynomial used is x16 x15 x2 1 When dummy information in the form of string of zer...

Page 447: ...n Table 599 Time synchronization command Code Command Length Sub Address Payload Description 0x07 SYNCH 0x04 0x00 MOSI SYNC1 SYNC2 SYNC3 SYNC4 CRC 16 MISO all zeros The master must transmit the SYNC c...

Page 448: ...2 Write Command Code Command Length Sub Address Payload Description 0x0D WRITE_SA Number of words to be written N SA MOSI DW1 DW2 DWN CRC 16 MISO all zeros he command is used to write a certain num be...

Page 449: ...the master using several options The status received by the master have invalid values using the response token The Read back command sent does not provide appropriate values in the received payload E...

Page 450: ...3 TERMINAL_FAULT Error 0 no fault 1 fault The bit flag a SPI terminal fault condi tion According to the module current state In SPI slave device this bit is enabled or disabled by SPI2 control registe...

Page 451: ...s to keep only one bus active for normal operation but using the redundant bus to achieve switchover The SPI protocol 2 implementa tion supports dedicated commands to achieve the activation and deacti...

Page 452: ...to zero to ensure forward compatibility 12 8 Word length WLEN The value of this field determines the length in bits of a transfer on the SPI bus Valid values are 0x03 to 0x1F Word length is WLEN 1 al...

Page 453: ...protocol 2 implementation 4 Status illegal command SIC This bit gets set to 1 when an illegal command is received A valid new command clears this status bit Valid only for SPI protocol 2 implementatio...

Page 454: ...ritten to zero to ensure forward compatibility 7 Write data interrupt enable WDE Valid only for SPI protocol 2 6 AMBA access error interrupt enable AE Valid only for SPI protocol 2 5 Change in config...

Page 455: ...RXN Valid only for SPI protocol 0 and 1 31 24 23 8 7 6 5 4 3 2 1 0 Key RESERVED MODSTAT RESERVED STF EN 0 0 0 0 0 0 0 0 0 1 w r rw rw rw rw r r rw rw 31 24 Safety code KEY Must be 0x68 when writing ot...

Page 456: ...contents of this register is a reflection of the time modified incremented using the sync and tick command respectively 31 0 CONFW 0x40000000 r 31 0 Configuration write address CONFW Defines the base...

Page 457: ...rm reset of individual SPI memory controller units SPIMCTRLx Software must enable clock and release reset described in section 26 before SPI memory controller units SPIMCTRLx configuration and transfe...

Page 458: ...bit in the core s status reg ister is set 46 2 2 I O area The I O area contains registers that are used when issuing commands directly to the memory device By default the core operates in System mode...

Page 459: ...uration register The read command bit field determines if normal or fast read is used The addi tional bit fields determine the length of address and dummy state The length of address and dummy bit fie...

Page 460: ...0 D1 D2 D4 D6 D8 D10 D12 D16 D17 D18 D20 D22 D24 D26 D28 CB2 D0 D3 D4 D7 D9 D10 D13 D15 D16 D19 D20 D23 D25 D26 D29 D31 CB3 D0 D1 D5 D6 D7 D11 D12 D13 D16 D17 D21 D22 D23 D27 D28 D29 CB4 D2 D3 D4 D5 D...

Page 461: ...s programmed through registers mapped into AHB address space Table 623 SPIMCTRL registers AHB address offset Register 0x00 Configuration register 0x04 Control register 0x08 Status register 0x0C Receiv...

Page 462: ...t is automatically cleared when the core has been reset Reset core should be used with care Writing this bit has the same effect as system reset Any ongoing transactions both on AMBA and to the SPI de...

Page 463: ...transferred an SPI command in user mode Reset value 0x00000000 31 8 7 0 RESERVED RDATA 0 nr R rw 31 8 RESERVED 7 0 Receive data RDATA Contains received data byte Reset value 0x000000UU where U is unde...

Page 464: ...tion 26 before configuration The system can be configured to protect and restrict access to the AMBA memory protection units 47 1 Overview The AMBA Protection unit allows user to define memory segment...

Page 465: ...system and DMA protection configuration and status registers APB address offset Registers Memory Protection Unit for system bus 0x80005000 0x80005000 Protection Configuration register 0x80005004 Prot...

Page 466: ...and 1 on APB bus 4 0x800051E4 Access control for DMA controller 2 and 3 on APB bus 4 0x800051E8 0x80005FFF Not used Memory Protection Unit for DMA bus 0x8010A000 0x8010A000 Protection Configuration r...

Page 467: ...and the range 0x80000000 to 0x8041FFFF Table 634 0x80005008 segment 0x10 PEA Protection Segment End Address register 31 0 EADDR 0x0 rw 31 0 EADDR End address of segment End address should be in the ra...

Page 468: ...s C8 24 N LEON3 Statistics Unit C7 22 T AHB Status Register C6 21 R On chip Instruction memory control registers C5 20 O CCSDS TDP SpaceWire I F C4 19 L IO Mux configuration register C3 18 CCSDS TDP S...

Page 469: ...0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 31 Memory contro...

Page 470: ...r Unit 1 A12 27 2 Memory Protection Unit for system bus A11 26 Clock gating configuration register unit 0 A10 25 C Clock gating configuration register unit 1 A9 23 O Configuration and test registers A...

Page 471: ...C8 24 N Stand alone DMA unit 2 C7 22 T Stand alone DMA unit 3 C6 21 R On chip Instruction memory control registers C5 20 O Memory protection for DMA bus C4 19 L IO Mux configuration register C3 18 PL...

Page 472: ...x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw...

Page 473: ...53B Interface C14 29 M CAN Controller with DMA C13 28 A CAN Controller with DMA C12 27 2 SPI to AHB Bridge C11 26 I2C to AHB Bridge C10 25 C Stand alone DMA unit 0 C9 23 O Stand alone DMA unit 1 C8 24...

Page 474: ...eric UART 4 C11 26 Generic UART 5 C10 25 C unused 24 O unused 23 N External ADC DAC Interface C7 22 T SPI Controller 0 C6 21 R SPI Controller 1 C5 20 O PWM generator C4 19 L General Purpose I O port 0...

Page 475: ...B12 B11 B10 R R B7 B6 B5 B4 B3 B2 B1 B0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 rw rw rw rw rw rw r r rw rw rw r...

Page 476: ...w rw rw rw rw rw rw rw rw rw rw rw r r rw rw rw rw rw rw rw rw 31 Generic UART 0 A15 30 D Generic UART 1 A14 29 M Generic UART 2 A13 28 A Generic UART 3 A12 27 2 Generic UART 4 A11 26 Generic UART 5 A...

Page 477: ...rw rw rw rw rw rw rw rw rw rw rw rw rw rw 31 ADC0 C15 30 ADC1 C14 29 C ADC2 C13 28 P ADC3 C12 27 U ADC4 C11 26 ADC5 C10 25 C ADC6 C9 24 O ADC7 C8 23 N DAC0 C7 22 T DAC1 C6 21 R DAC2 C5 20 O DAC3 C4 19...

Page 478: ...B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 rw rw rw rw rw rw rw r...

Page 479: ...0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 31 ADC0 B15 30 D ADC1 B14 29 M ADC2 B13 28...

Page 480: ...to change any register configuration of the memory protection 0 EN Enable Memory Protection of specified memory segments This is bit can be used to enable and disable all protected segments at the sam...

Page 481: ...20 19 18 17 16 15 1 0 G15 G14 G13 G12 G11 G10 G9 G8 G7 G6 G5 G4 G3 G2 G1 G0 Reserved EN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw r rw 31 G15 Grant SPI4S on t...

Page 482: ...us via the AHB2AHB bridge from the DMAAMBA bus 47 4 3 Protect clock gating unit from erroneous accesses To protect the clock gating from erroneous access the APB bridge can be programmed to deny all w...

Page 483: ...e access of the GR716 microcontroller in mission mode i e when DSU_EN is low The second unit is available via the IO switch matrix described in chapter 2 5 The second UART debug unit is setup via boot...

Page 484: ...o any address on the AMBAAHB bus 48 2 Operation 48 2 1 Transmission protocol The interface supports a simple protocol where commands consist of a control byte followed by a 32 bit address followed by...

Page 485: ...e the baud rate will be automatically discovered This is done by searching for the shortest period between two falling edges of the received data corresponding to two bit periods When three identical...

Page 486: ...tes that a framing error was detected Reset value 0 Input state RX Filtered input state Counter State TCNT Internal Counter state AHB UART status register 48 3 3 Table 659 0x0C SCALER AHB UART scaler...

Page 487: ...s in the MEM PROT unit See section 47 for more information 49 1 Overview The status registers store information about AMBAAHB accesses triggering an error response There is a status register and a fai...

Page 488: ...interrupt routine can acquire the address containing the correctable error from the failing address register and correct it When it is finished it resets the NE bit and the monitor ing becomes active...

Page 489: ...D 9 CE Correctable Error Set if the detected error was caused by a correctable error and zero otherwise 8 NE New Error Deasserted at start up and after reset Asserted when an error is detected Reset b...

Page 490: ...ns used for AMBA memory protection units configuration and control AHBTRACE unit 0 and 1 has identical configuration and status register Configuration and status reg isters for AHBTRACE1 are describe...

Page 491: ...The core can collect data for the events listed in table 664 below Table 663 AHB Trace buffer data allocation Bits Name Definition 127 96 Time tag The value of the time tag counter 95 AHB breakpoint h...

Page 492: ...time a master waits to be granted access to the bus after reception of a SPLIT response The core will only keep track of one master at a time This means that when a SPLIT response is detected the core...

Page 493: ...SERVED 22 16 Trace buffer delay counter DCNT 15 Bus select Available BA Set to 1 to indicate that the core has several buses connected The bus to trace is selected via the BSEL field 14 12 Bus select...

Page 494: ...he trace 1 Delay counter mode DM Indicates that the trace buffer is in delay counter mode 0 Trace enable EN Enables the trace buffer Table 667 0x000004 INDEX Trace buffer index register 31 11 10 4 3 0...

Page 495: ...the trace buf fer is frozen A mask register is associated with each breakpoint allowing breaking on a block of addresses Only address bits with the corresponding mask bit set to 1 are compared during...

Page 496: ...OM may be configured via bootstraps signals controlled by the user at reset The Boot ROM prepares an execution environment suitable for an Application Software ASW to take over the system This reduces...

Page 497: ...Boot ROM to level architecture The Processor Module Initialization sequence is triggered by reset condition It is responsible for ini tializing and self testing of on chip instruction and data memory...

Page 498: ...At 50MHz system clock wdg_timeout_app 600 Timeout in seconds set prior to application hand over from Boot ROM At 50MHz system clock wdg_timeout_remote 5 3600 Timeout in seconds waiting for remote acce...

Page 499: ...1 Only enabled if boot from primary option fails Note 2 Table only specify bits enabled by boot All other bits will remain as is after reset Note 3 SpaceWire PLL option is configured by is determined...

Page 500: ...BOOTRPT0 Boot Rom Report 31 10 9 7 6 5 4 2 1 0 Reserved CPY EXT RMT I D 0 rw rw rw rw rw rw 31 10 Reserved 9 7 ASW source copy CPY Status field for ASW source selected 0x0 None 0x1 SRAM chip select 0...

Page 501: ...word Application stack pointer sections 0 1 image section header Section layout defined in table below sections 1 7 image section header Section layout defined in table below cksum 16 bit word 16 bit...

Page 502: ...d to the unit accessing the GR716 Microcontroller via the selected remote control and access interface When remote control unit upload new software to the GR716 Microcontroller the remote unit can res...

Page 503: ...e control in Standby mode A remote host can access the AHB DMA bus via the AHBUART interface described in chapter TBD Information on which pins used to connect to the external UART bus is described in...

Page 504: ...I2C memory The Boot ROM only supports 10 bit device addressing on the I2C bus The external I2C memory is assumed to have 2 address bytes 51 6 4 External PROM SRAM memory The access time for external P...

Page 505: ...s features to automatically copy instruction and data sections before executing ASW 51 7 4 Redundant ASW load image All externally memory boot options have the capability to boot from redundant memory...

Page 506: ...low transfers or interfaces The watchdog timer reload register is accessible via remote interface and in case where software upload is extremely slow the remote software should be able to extend or re...

Page 507: ...configured as output ESD diode current max 10mA 10 10 mA IDIO_IN Digital input current 10 10 mA IDIO_OUT Digital output current when configured as HiZ 10 10 mA IDIO_OUT Digital output current when con...

Page 508: ...I O cells in terms of the Human Body Model Note 7 VDDAPLL shall not be connected except for external decoupling to ground Note 8 Voltage may not exceed 4 0V Note 9 5 11k 3 5 EOL The tolerance of the...

Page 509: ...2 Case Temperature 55 125 C SLIN_LVTTL Slew rate of all LVTTL inputs 1 0 V ns SLIN_LVDS Slew rate of all LVDS inputs 1 5 V ns Note 1 Within recommended operating conditions all functionality and perf...

Page 510: ...IO I O Supply Current 2 4 100 mA IDDIOE I O Disable Current IO supplied via LDO 10 mA IDDIOS_LVDS_E I O Supply Current 5 4 30 mA IDDIOS_LVDS_D I O Supply Current 6 4 1 10 mA IDDXO XO Supply Current FX...

Page 511: ...160 uA VIN 0V 10 uA IILEAK_3 2 Input Leakage Current GPIO Internal pull up VIN VDDIO 10 uA VIN 0V 160 uA IILEAK_4 3 Input Leakage Current Internal pull down VIN VDDIO 160 uA VIN 0V 10 uA IILEAK_5 4 In...

Page 512: ...differential input voltage hysteresis Note 4 Failure to comply with the differential input thresholds will make the receiver logic condition unknown For noisy environment or protection from various f...

Page 513: ...it Output current 12 mA CO_LVDS LVDS Output capacitance 5 pF Note 1 Recommended operating conditions see chapter 52 2 Note 2 LVDS outputs are terminated with 100 Ohm Note 3 LVDS drivers fully complian...

Page 514: ...er schematics Simplified input and output buffer schematics presented in this chapter is applicable within absolute maximum rating conditions see chapter 52 1 52 6 1 Simplified Bidir buffer with analo...

Page 515: ...1 29 518 www cobham com gaisler GR716 52 6 2 Simplified LVDS input buffer schematic 52 6 3 Simplified LVDS output buffer schematic Figure 93 Simplified LVDS input buffer schematic Figure 94 Simplified...

Page 516: ...inearity Without DEM virt gnd load 2 3 LSB With DEM virt gnd load 1 3 3 Without DEM Rload 0 2 5V 3 3 With DEM Rload 0 2 5V 2 3 3 DNL Differential non linearity Without DEM 1 3 LSB With DEM 0 8 3 PSRR...

Page 517: ...taken TBD TBD ns VDDAADC Supply voltage 3 0 3 6 V Single ended analog input FS Full scale With reference to VSSAADC Vref 1 000V TBD 2 5 TBD V Gain error With reference to VSSAADC Vref 1 000V 2 2 VINO...

Page 518: ...Vref 1 00V V Gain x1 TBD 2 TBD Gain x2 TBD 1 TBD Gain x4 TBD 0 5 TBD GPreAmp Gain of pre amp Gain x1 1 2 Gain x2 2 2 Gain x4 4 2 Gain error of ADC TBD VP A OFFS Input offset voltage of pre amp exclud...

Page 519: ...sup 20mVpp 100kHz TBD TBD IVD DA_ADC Current consumption Operating at fS max 10 30 mA Operating at fS min TBD TBD Shutdown TBD TBD Note 1 VDDAADC VSSAADC 3 0 3 6V typical values are at 25C min max val...

Page 520: ...current 2 mA VDDAREF Supply voltage 3 0 3 6 Note 1 Unless otherwise noted VDDAREF VSSAREF 3 0 3 6V typical values are at 25C min max values are at full temperature range Note 2 Determined as IRref VRr...

Page 521: ...consumption No shutdown mode available 100 TBD uA Note 1 Unless otherwise noted VDDCORE GNDCORE 0 1 2 0V typical values are at 25C min max values are at full temperature range Symbol Parameter Conditi...

Page 522: ...ing parameters are defined in table 693 Table 693 System clock timing parameters Name Parameter Reference edge Min Max Unit tCLK0 Clock period 20 1 ns Clock period 3 4 205 200 ns tCLK1 Clock high low...

Page 523: ...2 0 40 x tSP WCLK0 0 60 x tSP WCLK0 ns tSPWCLK2 Clock cycle jitter 1 100 100 ps Clock cycle jitter 2 2 ns Note 1 Only applicable when PLL is bypassed see section 4 Note 2 Only applicable when PLL use...

Page 524: ...only available via IO mux see chapter 2 5 Table 697 External PacketWire clock timing parameters Name Parameter Reference edge Min Max Unit tPWCLK0 Clock period 100 ns tPWCLK1 Clock high low pulse len...

Page 525: ...RSTIN0 before RESET_IN_N is de asserted Note 3 The internal reset for the system clock domain is released 5 x tCLK0 after RESET_IN_N is de asserted The internal reset for the SpaceWire clock domain is...

Page 526: ...CLK edge 4 ns tSPI2 Input to clock setup Rising CLK edge 4 ns Note The SPI_SCK SPI_MOSI and SPI_SLVSEL inputs are re synchronized internally and does not have to meet any setup or hold requirements T...

Page 527: ...0 Table 703 SPI interface timing parameters Name Parameter Reference edge Min Max Unit tSPI4S0_LVDS Clock to output delay Rising SPI4S_CLK edge 0 15 ns tSPI4S1_LVDS Input to clock hold Rising SPI4S_CL...

Page 528: ...ameters Name Parameter Reference edge Min Max Unit tSPW1 Output data bit period 10 500 ns tSPW2 Data strobe output skew jitter 0 150 ps tSPW3 Input data bit period 10 500 ns tSPW4 Data strobe input sk...

Page 529: ...ference edge Min Max Unit tSPW1_LVDS Output data bit period 10 500 ns tSPW2_LVDS Data strobe output skew jitter 0 150 ps tSPW3_LVDS Input data bit period 10 500 ns tSPW4_LVDS Data strobe input skew ji...

Page 530: ...are re synchronized to the internal system clock with a tCLK0 period The signals do not have to meet any setup or hold requirements Table 707 Timing parameters VDD 1 8V 0 15V VDDIO 3 3V 0 3V Tcase 55...

Page 531: ...he core to operate in Fast or Standard Mode the timing charac teristics in the I2C bus specification apply The maximum tCLK0 period for proper operation is 50 ns Note 2 The I2CSCL and I2CSDA inputs ar...

Page 532: ...O 3 3V 0 3V Tcase 55 C to 125 C Name Parameter Reference edge Min Max Unit tGRPWTX0 bit period rising SYS_CLK edge 100 ns tGRPWTX1 data active abort input to clock hold rising SYS_CLK edge 5 ns tGRPWT...

Page 533: ...ns tFTMCTRL5 clock to data tri state delay rising clk edge 1 TBD 3 20 3 ns tFTMCTRL6 clock to output delay rising clk edge 1 0 2 20 3 ns tFTMCTRL7 data input to clock setup rising clk edge 1 5 3 ns t...

Page 534: ...PBUART0 clock to output delay rising clk edge 0 1 20 2 ns tAPBUART1 input to clock hold rising clk edge 3 ns tAPBUART2 input to clock setup rising clk edge 3 ns 1 Guaranteed by design not tested 2 Ver...

Page 535: ...chronized internally These signals do not have to meet any setup or hold requirements As the dsu_en signal controls clock gating for the Debug AHB bus the signal s value should be kept con stant from...

Page 536: ...cillator negative input VREFBUF out 30 2 External analog precision voltage refer ence VREF 4 out 31 External BandGap reference Connect to external capacitor RREF 5 out 32 External BandGap reference Co...

Page 537: ...2 7 8 8 GPIO 42 inout 26 LVTTL 7 2 7 8 8 GPIO 43 inout 27 LVTTL 7 2 7 8 8 GPIO 44 inout 28 LVTTL 7 2 7 8 8 GPIO 45 inout 34 LVTTL 7 2 7 8 8 General purpose IO with analog DAC output capabilities See s...

Page 538: ...VTTL 2 8 8 GPIO 50 inout 65 LVTTL 2 8 8 GPIO 51 inout 66 LVTTL 2 8 8 GPIO 52 inout 67 LVTTL 2 8 8 GPIO 53 inout 68 LVTTL 2 8 8 GPIO 54 inout 69 LVTTL 2 8 8 GPIO 55 inout 70 LVTTL 2 8 8 GPIO 56 inout 7...

Page 539: ...ote 6 Connect to ground via resistance of 10 Kohm resistor Note 7 Applies only for digital functionality Note 8 Parameter is programmable when digital functionality is selected for pin Note 9 In singl...

Page 540: ...GR716 DS UM May 2019 Version 1 29 543 www cobham com gaisler GR716 53 3 Mechanical package drawings Figure 117 132 CQFP package top view...

Page 541: ...0 23 0 329 mm b2 Width of lead when closest to ceramic bar 0 15 0 25 mm c 0 075 0 175 mm D E 50 85 mm D1 E1 30 73 mm D2 E2 23 88 24 26 mm D3 E3 20 32 mm D4 E4 20 2 mm e 0 635 mm L1 Length of lead from...

Page 542: ...for new orders Note 3 Marked with GR716 XX CQ132 on the lid Table 718 Ordering legend Designator Option Description Product GR716 Radiation Tolerant LEON3 Microcontroller Temperature Range M 55 C to...

Page 543: ...that it locks the IOs direction when it triggers This together with the faulty state after power on implies that the supported boot alternatives are limited IO direction is only locked for GR716 XX CQ...

Page 544: ...behave according to the description in section 20 7 when MCFG1 ROMBANKSZ 0xA When MCFG1 ROMBANKSZ 0xA then romsn 1 0 will never be activated ROMBANKSZ 0x0 0x09 behave as per the description in sectio...

Page 545: ...GR716 DS UM May 2019 Version 1 29 549 www cobham com gaisler GR716 Workaround n a...

Page 546: ...troller with support for 4 byte address ID GR716 FEATURE 20190409 Contact support gaisler com for more information 56 2 5 SpaceWire TDP synchronization to PPS 1Hz input ID GR716 FEATURE 20190410 Conta...

Page 547: ...sponsibility or liability arising out of the application or use of any product or service described herein except as expressly agreed to in writing by Cobham nor does the purchGR716 DS UMase lease or...

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