GR716-DS-UM, May 2019, Version 1.29
379
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GR716
Reads from the I
2
C configuration address will return the current value of the configuration register.
Writes to the I
2
C configuration address will affect the writable bits in the configuration register.
37.2.5 AHB accesses
All AMBA accesses are done in big endian format. The first byte sent to or from the slave is the most
significant byte.
To write a word on the AHB bus the following I2C bus sequence should be performed:
1. Generate START condition
2. Send I2C memory address with the R/W bit set to ‘0’.
3. Send four byte AMBA address, the most significant byte is transferred first
4. Send four bytes to write to the specified address
5. If more than four consecutive bytes should be written, continue to send additional bytes, other-
wise go to 6.
6. Generate STOP condition
To perform a read access on the AHB bus, the following I2C bus sequence should be performed:
1. Generate START condition
2. Send I2C memory address with the R/W bit set to ‘0’.
3. Send four byte AMBA address, the most significant byte is transferred first
4. Generate (repeated) START condition
5. Send I2C memory address with the R/W bit set to ‘1’.
6. Read the required number of bytes and NACK the last byte
7. Generate stop condition
During consecutive read or write operations, the core will automatically increment the address. The
access size (byte, halfword or word) used on AHB is set via the HSIZE field in the I2C2AHB config-
uration register.
The core always respects the access size specified via the HSIZE field. If a write operation writes
fewer bytes than what is required to do an access of the specified HSIZE then the write data will be
dropped, no access will be made on AHB. If a read operation reads fewer bytes than what is specified
by HSIZE then the remaining read data will be dropped at a START or STOP condition. This means,
for instance, that if HSIZE is “10” (word) the core will perform two word accesses if a master reads
one byte, generates a repeated start condition, and reads one more byte. Between these two accesses
the address will have been automatically increased, so the fist access will be to address
n
and the sec-
ond to address
n+4
.
The automatic address increment means that it is possible to write data and then immediately read the
data located at the next memory position. As an example, the following sequence will write a word to
address 0 and then read a word from address 4:
1. Generate START condition
2. Send I2C memory address with the R/W bit set to ‘0’.
3. Send four byte AMBA address, all zero.
4. Send four bytes to write to the specified address
2
NACK (NACK) - Use NACK instead of clock stretching. See documentation in sec-
1:0
AMBA access size (HSIZE) - Controls the access size that the core will use for
AMBA accesses. 0: byte, 1: halfword, 2: word. HSIZE = “11” is illegal.
Reset value: 0x02
Table 505.
I2C2AHB configuration register