GR716-DS-UM, May 2019, Version 1.29
374
www.cobham.com/gaisler
GR716
36.3.3
Table 499.
0x08 - CONFIG - Configuration register
Configuration Register
36.3.4
Table 500.
0x0C - CATCHCFG - Timer latch configuration register
Timer Latch Configuration Register
36.3.5
Table 501.
0xn0, when n selects the times - TCNTVALn - Timer n counter value register
Timer N Counter Value Register
31
23 22
16 15 14 13 12 11 10
9
8
7
3
2
0
“000..0”
TIMEREN
R
EV ES EL EE DF SI
RESERVED
TIMERS
0
0
0
0
0
0
0
0
1
*
7
r
rw
r
rw rw rw rw rw
r
r
r
31: 23
Reserved. Always reads as ‘000...0’.
22: 16
Enable bits for each timer. Writing ‘1’ to one of this bits sets the enable bit in the corresponding tim-
ers control register. Writing ‘0’ has no effect to the timers. bit[16] corresponds to timer0, bit[17] to
timer 1,...
15: 14
Reserved
13
External Events (EV). If EV is set to 0 then the latch and set events are taken from the least signifi-
cant 32 bit of the interrupt bus, otherwise they are from some of the most significant ones and some
external signals (see table 35.3.4).
12
Enable set (ES). If set, on the next matching interrupt, the timers will be loaded with the correspond-
ing timer reload values. The bit is then automatically cleared, not to reload the timer values until set
again.
11
Enable latching (EL). If set, on the next matching interrupt, the latches will be loaded with the corre-
sponding timer values. The bit is then automatically cleared, not to load a timer value until set again.
10
Enable external clock source (EE). If set the prescaler is clocked from the external clock source.
9
Disable timer freeze (DF). If set the timer unit can not be freezed, otherwise signal GPTI.DHALT
freezes the timer unit.
8
Separate interrupts (SI). Reads ‘1’ if the timer unit generates separate interrupts for each timer, oth-
erwise ‘0’. Read-only.
7: 3
Reserved
2: 0
Number of implemented timers. Read-only.
31
0
LATCHSEL
0
rw
31: 0
This field specifies which bits of the interrupt bus or of the external signals (depending on EV field
in table 35.3.3) cause the set and latch events. If EV is 0, the latching is done based on events on the
31:0 bits of the interrupt bus with a direct mapping. If the EV field is ‘1’, the bits 29:0 correspond to
the 61:32 bits of the interrupt bus, while the bit 30 corresponds to the TICKOUT signal from the
SpaceWire Interface (see chapter 33) and the bit 31 corresponds to the rtsync signal from the MIL-
STD-1553B / AS15531 Interface (see chapter 23).
32-1
0
TCVAL
0
rw
32-1: 0
Timer Counter value. Decremented by 1 for each prescaler tick.
Any unused most significant bits are reserved. Always reads as ‘000...0’.
