GR716-DS-UM, May 2019, Version 1.29
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GR716
trol Register. If KS is set, only the first assertion and acknowledge of an interrupt is stamped. Soft-
ware must then clear the S1 and S2 fields for a new timestamp to be taken. If Keep Stamp is disabled
(KS field not set), the controller will update the Interrupt Assertion Timestamp Register every time
the selected interrupt line is asserted. In this case the controller will also automatically clear the S2
field and also update the Interrupt Acknowledge Timestamp register with the current value when the
interrupt is acknowledged.
40.2.5 Interrupt timestamping usage guidelines
Note that KS = ‘0’ and a high interrupt rate may cause the Interrupt Assertion Timestamp register to
be updated (and the S2 field reset) before the processor has acknowledged the first occurrence of the
interrupt. When the processor then acknowledges the first occurrence, the Interrupt Acknowledge
Timestamp register will be updated and the difference between the two Timestamp registers will not
show how long it took the processor to react to the first interrupt request. If the interrupt frequency is
expected to be high it is recommended to keep the first stamp (KS field set to ‘1’) in order to get reli-
able measurements. KS = ‘0’ should not be used in systems that include cores that use level interrupts,
the timestamp logic will register each cycle that the interrupt line is asserted as an interrupt.
In order to measure the full interrupt handling latency in a system, software should also read the cur-
rent value of the Interrupt Timestamp Counter when entering the interrupt handler. In the typical case,
a software driver’s interrupt handler reads a status register and then determines the action to take.
Adding a read of the timestamp counter before this status register read can give an accurate view of
the latency during interrupt handling.
The interrupt controller listens to the system interrupt vector when reacting to interrupt line assertions.
This means that the Interrupt Assertion Timestamp Register(s) will not be updated if software writes
directly to the pending or force registers. To measure the time required to serve a forced interrupt, read
the value of the Interrupt Timestamp counter before forcing the interrupt and then read the Interrupt
Acknowledge Timestamp and Interrupt Timestamp counter when the processor has reacted to the
interrupt.
40.2.6 Watchdog
The interrupt controller supports for asserting a bit in the controller’s Interrupt Pending Register when
an external watchdog signal is asserted. This functionality can be used to implement a sort of soft
watchdog for one or several processor cores. The controller’s Watchdog Control Register contains a
field that shows the number of external watchdog inputs supported and fields for configuring which
watchdog inputs that should be able to assert a bit in the Interrupt Pending Register. The pending reg-
ister will be assigned in each cycle that a selected watchdog input is high. Therefore it is recom-
mended that the watchdog inputs are connected to sources which send a one clock cycle long pulse
when a watchdog expires. Otherwise software should make sure that the watchdog signal is deas-
serted before re-enabling interrupts during interrupt handling.
The GR716 microcontroller supports soft watchdog events from GPTIMER0 timer 6 and GPTIMER0
timer 7.
40.2.7 Dynamic processor reset start address
The interrupt controller can be used to start processor execution from a specified start address. The
interface provided to accomplish this is:
•
Error mode status register
•
Processor boot address registers
The register interface allows software to force a processor into debug or error mode. This means that
the interface can be used to stop (and restart) a processor. Registers are available to allow starting a
halted processor from an arbitrary 8 byte aligned entry point. The processor can be started with the