GR716-DS-UM, May 2019, Version 1.29
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GR716
4
Clocking
Up to six unique external clock sources connected on five external input pins: SYS_CLK, SPW_-
CLK, PWRX_CLK, GR1553_CLK, SPI4S_CLK, PWM_CLK sources can be used for generating
different clocks in the GR716 Microcontroller. Internal ADC and DAC clock generation is also sup-
ported to control asynchronous interface for the ADC and DAC.
Note that external PacketWire
clock is only accessible via the IO switch matrix
The internal ADC_CLK is generated via control registers for the internal ADC, see chapter 12.
There are four internal DAC_CLK clocks. Each DAC_clock is generated individually via control reg-
isters, see chapter 15.
The SYS_CLK pin is used as the main system clock, and can be selected to directly drive the clock
network without PLL. The SYS_CLK is selected by default as system clock. The system clocks shall
always be running during reset and normal operation.
The SPW_CLK pin is the external SpaceWire clock, and it can be used to generate the internal clocks
directly or multiplied with a PLL, depending on the value of the configuration registers in PLL con-
figuration block, see chapter 10.
The GR1553_CLK pin is the external MIL-1553B 20 MHz clock and can be used if MIL-1553B
interface requires external clock.
The PWRX_CLK pin is the external PacketWire Reciever clock and is used if PacketWirer receiver
interface is enabled.
The microcontroller PLL can be used to generate frequencies required for SpaceWire, 1553B or the
system. The lowest frequency to be used with the integrated PLL is 4 MHz to be able to meet jitter
performance for SpaceWire (with ideal supply).
Clock distribution and configuration in the microcontroller is shown in figure 5. In figure 5 the ’blue’,
’green’ and ’grey’ boxes represents logic. External pins are marked with ’names’ for cross reference
to the pin list in section 3.3. Control registers accessible via software or external boot-straps in order
to setup and configure clocks in the system are named using the format
<register name>.<bitfield>
.
Table 37.
Clock inputs
Clock input
Description
Frequency Range
ADC_CLK
ADC clock generated from internal logic used for clocking and con-
trol of internal ADC
up to 2 MHz
DAC_CLK
DAC clock generated from internal logic used for clocking and con-
trol of the internal DAC
up to 3 MHz
SYS_CLK
System clock input
1 - 50 MHz
5)
SPW_CLK
SpaceWire clock
4 - 100 MHz
2)
GR1553_CLK
MIL-STD-1553B interface clock (Only valid via PIN muxing)
20 MHz
3)
SPI4S_CLK
SPI for Space clock
up to 25 MHz
3)
PWRX_CLK
PacketWire receive clock
up to 12.5 MHz
1)
PWTX_CLK
PacketWire loop-back clock for test purpose
up to 12.5 MHz
1)
PWM_CLK
PWM clock
up to 100MHz
Note 1: Frequency shall be equal or lesser than system clock frequency divided by 4
Note 2: Duty cycle for SpaceWire clock shall be set to 50/50 for best jitter performance
Note 3: Duty cycle for MIL-STD-1553B clock shall be at least 40%
Note 4: Frequency shall be equal or lesser than system clock frequency divided by 2
Note 5: System clock must at all time be supplied to the system