
LeveLine
®
Instruction Manual
10401-01026 Rev D
6.15.4. Serial Communication Parity
Holding register 4 can be set to select the communication parity type. Its factory default
value is 2 (even parity). Note that if this register is set to a new value, the change in
communication speed will occur after the response has been transmitted. Note also that
when set to 0 (no parity), the parity bit in each transmitted byte frame is replaced with an
extra stop bit.
6.15.5. Input Registers
The input registers hold the measurements read from the LeveLine
®
.
6.16. MODBUS Cyclic Redundancy Check
The cyclic redundancy check is calculated on the entire contents of the packet, starting with
the slave address and ending with the last byte before the start of the CRC field.
The CRC field is composed of the two bytes of the CRC value, least significant byte first,
most significant byte second. (Note that this is the opposite order to multi-byte values in the
<data> field of the packet.)
The algorithm for calculating the CRC is as follows:
Set crc = 0xFFFF
For each message character c:
Set crc = crc XOR c
Repeat 8 times:
If least significant bit of crc is 1,
Shift crc right by one bit
Set crc = crc XOR 0xA001
Otherwise,
Shift crc right by one bit
© 2019 Aquaread
®
Ltd.
www.aquaread.com
Page 83 of 90