Samsung S3C6400X, Руководство пользователя, Страница: 919 / 1189

PRELIMINARY
S3C6400X RISC MICROPROCESSOR HSMMC CONTROLLER
27-43
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
CLOCK CONTROL REGISTER
At the initialization of the Host Controller, the Host Driver sets the SDCLK Frequency Select according to the
Capabilities register .
Register Address R/W Description Reset Value
CLKCON0 0x7C20002C R/W Command Register (Channel 0) 0x0
CLKCON1 0x7C30002C R/W Command Register (Channel 1) 0x0
CLKCON2 0x7C40002C R/W Command Register (Channel 2) 0x0
Name Bit Description Initial
Value
[15:8]
SDCLK Frequency Select
This register is used to select the frequency of SDCLK pin. The frequency is not
programmed directly; rather this register holds the divisor of the Base Clock
Frequency For SD Clock in the Capabilities register. Only the following settings
are allowed.
80h base clock divided by 256
40h base clock divided by 128
20h base clock divided by 64
10h base clock divided by 32
08h base clock divided by 16
04h base clock divided by 8
02h base clock divided by 4
01h base clock divided by 2
00h base clock (10MHz-63MHz)
Setting 00h specifies the highest frequency of the SD Clock. Setting multiple bits,
the most significant bit is used as the divisor. But multiple bits must not be set. The
two default divider values can be calculated by the frequency that is defined by the
Base Clock Frequency For SD Clock in the Capabilities register.
(1) 25MHz divider value
(2) 400KHz divider value
According to the SD Physical Specification Version 1.01 and the SDIO Card
Specification Version 1.0, maximum SD Clock frequency is 25MHz, and never
exceeds this limit.
The frequency of SDCLK is set by the following formula:
Clock Frequency = (Base Clock) / divisor
Therefore, select the smallest possible divisor which results in a clock frequency
that is less than or equal to the target frequency.
For example, if the Base Clock Frequency For SD Clock in the Capabilities
register has the value 33MHz, and the target frequency is 25MHz, then selecting
the divisor value of 01h will yield 16.5MHz, which is the nearest frequency less than
or equal to the target. Similarly, to approach a clock value of 400KHz, the divisor
value of 40h yields the optimal clock value of 258KHz.
0
[7:4]
Reserved
[3] External Clock Stable 0