PRELIMINARY
DMA
S3C6400 RISC MICROPROCESSOR
11-24
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Table 11-22. Protection bits
Bits
Description
Purpose
0 Privileged
or
User
Indicates that the access is in User, or privileged mode:
0 = User mode
1 = privileged mode.
This bit controls the AHB
HPROT[1]
signal.
1 Bufferable
or
not bufferable
Indicates that the access is bufferable, or not bufferable:
0 = not bufferable
1 = bufferable.
This bit indicates that the access is bufferable. This bit can, for example, be used to indicate
to an AMBA bridge that the read can complete in zero wait states on the source bus without
waiting for it to arbitrate for the destination bus and for the slave to accept the data.
This bit controls the AHB
HPROT[2]
signal.
2 Cacheable
or
not cacheable
Indicates that the access is cacheable or not cacheable:
0 = not cacheable
1 = cacheable.
This indicates that the access is cacheable. This bit can, for example, be used to indicate to
an AMBA bridge that when it saw the first read of a burst of eight it can transfer the whole
burst of eight reads on the destination bus, rather than pass the transactions through one at a
time.
This bit controls the AHB
HPROT[3]
signal.
Channel control register, DMACCxControl1
The eight read/write DMACCxControl1 registers contain DMA channel control information such as the transfer size.
Each register is programmed directly by software before the DMA channel is enabled. When the channel is enabled
the register is updated by following the linked list when a complete packet of data has been transferred.
Reading the register whilst the channel is active does not give useful information. This is because by the time that
software has processed the value read, the channel might have progressed. It is intended to be read only when a
channel has stopped.
Table 11-23 shows the bit assignment of a DMACCxControl1 register.
Table 11-23. Bit Assignment of DMACCxControl1 register (continued)
DMACCxControl
Bits
Type
Function
TransferSize
[24:0]
R/W
Transfer size. For writes, this field indicates the number of (Source width)
transfers to perform when the DMA controller is the flow controller.
For reads, the transfer size indicates the number of transfers completed
on the destination bus. Reading the register when the channel is active
does not give useful information, as by the time that the software has
processed the value read, the channel might have progressed. It is
intended to be used only when a channel is enabled and then disabled.
If the DMAC controller is not the flow controller the transfer size value is
not used.