Samsung S3C6400X, Руководство пользователя, Страница: 346 / 1189

PRELIMINARY
S3C6400X RISC MICROPROCESSOR SECURITY SUB-SYSTEM
13-9
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
SECURITY SUB-SYSTEM RX FIFO MODULE
FIFO-RX CONTROL REGISTER
Register Address R/W Description Reset Value
FRx_Ctrl 0x7D40_0000 R/W
FIFO-Rx Control/Status Reg. (Only MSB 16-bit readable) 0x0420_0000
FRx_Ctrl Bit Description Initial State
FRx_WrPrivError [31]
Sets to 1 if write access to FIFO-Rx has resulted in a
privilege error (e.g. Host or the command are not allowed to
access FIFO-Rx). 0b
FRx_RdPrivError [30]
Sets to 1 if read access to FIFO-Rx has resulted in a privilege
error (e.g. Host or the command are not allowed to access
FIFO-Rx). 0b
Reserved [29] Reserved 0b
FRx_Full [27] Sets to 1 if FIFO-Rx buffer (FRx_WrBuf) is full. 0b
FRx_Empty [26] Sets to 1 if FIFO-Rx buffer (FRx_WrBuf) is empty. 1b
FRx_Done [25]
Sets to 1 if FIFO-Rx has finished transferring FRx_MLen
words of data to the destination. 0b
FRx_Running [24]
Sets to 1 if FIFO-Rx is transferring data to the destination or
waiting for destination input buffer is ready. Sets to 1 when
FRx_Start bit resets to 0. 0b
FRx_Wd2Write [23:16]
Number of words that can be written to FIFO memory
(FRx_WrBuf)
0x00
FRx_Wd2Read [15:8]
Number of words that can be read from FIFO memory
(FRx_WrBuf)
0x00
FRx_Dest_Module [7:6]
Destination module selection.
( 00 : AES, 01:DES/3DES, 10: SHA-1/PRNG, 11: Not
Used )
0b
FRx_Host_Rd_En [5] Enables Host read from FRx_Ctrl[31:16] and FRx_MLenCnt. 0b
FRx_Host_Wr_En [4] Enables Host write to FRx_WrBuf 0b
FRx_Sync_Tx [3] When enabled, FIFO-Rx waits for FIFO-Tx to retrieve output
data from source module before transferring data to the
destination module. 0b
FRx_Reset [2] Stops current FIFO-Rx transfer and resets FSM and all the
register. 0b
FRx_ERROR_En [1] Enables ERROR response via HRESP port when host tries to
access FIFO-Rx and access is not enabled by FRx_Ctrl[4] or
[5]. 0b
FRx_Start [0] FIFO-Rx transfer start bit. Resets to 0 when internal FSM
starts transferring data to destination.
0b