Samsung S3C6400X, Руководство пользователя, Страница: 8 / 1189

PRELIMINARY
S3C6400
RISC MICROPROCESSOR PRODUCT OVERVIEW
1-5
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
1.1.3 Memory Subsystem
The S3C6400 microprocessor provides the following Memory Subsystem features:
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High bandwidth Memory Matrix subsystem
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Two independent external memory ports (1 Static-DRAM Hybrid Memory port and 1 DRAM ports)
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Matrix architecture increases overall bandwidth with the simultaneous access capability
1.1.3.1 Static-DRAM Hybrid Memory port configurable to support the following memory types:
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Support SRAM/ROM/NOR Flash Interface
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x8 or x16 data bus
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Address range support: max. 26-bits (128MB)
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Support byte and half-word access
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OneNAND Flash interface
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x16 data bus
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NAND Flash Boot Loader
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System can be booted from NAND when system initialization begins
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Reset of memory area is used for storing user data
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Supports both SLC and MLC NAND Flash memory
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CF interface
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Compatible with CF+ and CompactFlash Spec.(Rev 3.0)
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SDRAM Interface
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x16 data bus
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1.8/ 2.5V interface voltage
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Density support:
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Memory Port0 : up to 1Gb
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Memory Port1 : up to 2Gb
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Mobile SDRAM Interface
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x16 data bus with 133Mbps/pin data rate
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133MHz address and command bus speed
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1.8/ 2.5V interface voltage
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Density support: up to 2Gb
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Mobile SDRAM feature support:
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DS (Driver Strength Control)
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TCSR (Temperature Compensated Self-Refresh Control)
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PASR (Partial Array Self-Refresh Control)
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Mobile DDR Interface
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x16 data bus with 266Mbs/pin double data rate (DDR)
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1.8/ 2.5V interface voltage
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Density support: up to 2Gb