Samsung S3C6400X, Руководство пользователя, Страница: 116 / 1189

PRELIMINARY
DRAM CONTROLLER S3C6400X RISC MICROPROCESSOR
5-10
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
CAS Half cycle [0]
Encodes whether the CAS latency is half a memory clock cycle
more than the value given in bits[3:1]
0 = Zero cycle offset to value in [3:1]. [0] is forced to 0 in MDDR
and SDR mode.
1 = Half cycle offset to the value in [3:1].
0
T_DQSS REGISTER
Register Address R/W Description Reset Value
P0T_DQSS 0x7E000018 R/W 16-bit DRAM controller t_DQSS register 0x1
P1T_DQSS 0x7E001018 R/W 32-bit DRAM controller t_DQSS register 0x1
PnT_DQSS Bit Description Initial State
[31:2] Read undefined. Write as Zero
t_DQSS [1:0] Write to DQS in memory clock cycles. 1
T_MRD REGISTER
Register Address R/W Description Reset Value
P0T_MRD 0x7E00001C R/W 16-bit DRAM controller t_MRD register 0x02
P1T_MRD 0x7E00101C R/W 32-bit DRAM controller t_MRD register 0x02
PnT_MRD Bit Description Initial State
[31:7] Read undefined. Write as Zero
t_MRD [6:0] Set mode register command time in memory clock cycles. 0x02
T_RAS REGISTER
Register Address R/W Description Reset Value
P0T_RAS 0x7E000020 R/W 16-bit DRAM controller t_RAS register 0x7
P1T_RAS 0x7E001020 R/W 32-bit DRAM controller t_RAS register 0x7
PnT_RAS Bit Description Initial State
[31:4] Read undefined. Write as Zero
t_RAS [3:0] Set RAS to precharge delay in memory clock cycles. 0x7