PRELIMINARY
S3C6400X RISC MICROPROCESSOR
USB2.0 HS OTG
26-53
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Bit 0 for IN endpoint 0, bit 15 for endpoint 15
DEVICE ALL ENDPOINTS INTERRUPT MASK REGISTER (DAINTMSK)
The Device Endpoint Interrupt Mask register works with the Device Endpoint Interrupt register to interrupt the
application when an event occurs on a device endpoint. However, the Device all Endpoints Interrupt register bit
corresponding to that interrupt will still be set.
·
Mask interrupt : 1’b0
·
Unmask interrupt : 1’b1
Register
Address
R/W
Description
Reset Value
DAINTMSK 0x7C00_081
C
R/W
Device ALL Endpoints Interrupt Mask Register
32 bits
DAINTMSK
Bit
R/W
Description
Initial State
OutEPMsk
[31:16]
R_W
OUT EP Interrupt Mask Bits
One bit per OUT endpoint :
Bit 16 for OUT EP 0, bit 31 for OUT EP 15
16’h0
InEpMsk
[15:0]
R_W
IN EP Interrupt Mask Bits
One bit per IN endpoint :
Bit 0 for IN EP 0, bit 15 for IN EP 15
16’h0
DEVICE IN TOKEN SEQUENCE LEARNING QUEUE READ REGISTER 1 (DTKNQR1)
The queue is 4 bits wide to store the endpoint number. A read from this register returns the first 5 endpoint entries
of the IN Token Sequence Learning Queue. When the Queue is full, the new token is pushed into the queue and
oldest token is discarded.
Register
Address
R/W
Description
Reset Value
DTKNQR1
0x7C00_0820
R
Device IN Token Sequence Learning Queue Read
Register 1
32 bits
DTKNQR1
Bit
R/W
Description
Initial State
EPTkn
[31:8]
RO
Endpoint Token
Four bits per token represent the endpoint number of
the token :
·
Bits [31:28] : Endpoint number of Token 5
·
Bits [27:24] : Endpoint number of Token 4
···
·
Bits [15:12] : Endpoint number of Token 1
·
Bits [11:8] : Endpoint number of Token 0
24’h0
WrapBit
[7]
RO
Wrap Bit
This bit is set when the write pointer wraps. It is
cleared when the learning queue is cleared.
1’b0