Samsung S3C6400X, Руководство пользователя, Страница: 262 / 1189

PRELIMINARY
S3C6400 RISC MICROPROCESSOR GPIO
10-
41
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
PORT Q CONTROL REGISTERS
There are five control registers including GPQCON, GPQDAT, GPQPUD, GPQCONSLP and GPQPUDSLP in the
Port Q Control Registers.
Register Address R/W Description Reset Value
GPQCON 0x7F008180 R/W Port Q Configuration Register 0x0002AAAA
GPQDAT 0x7F008184 R/W Port Q Data Register Undefined
GPQPUD 0x7F008188 R/W Port Q Pull-up/down Register 0x0
GPQCONSLP 0x7F00818C R/W Port Q Sleep mode Configuration Register 0x0
GPQPUDSLP 0x7F008190 R/W Port Q Sleep mode Pull-up/down Register 0x0
GPQCON Bit Description Initial State
GPQ0 [1:0] 00 = Input 01 = Output
10 = MEM0_RAS 11 = Ext. Interrupt Group9[0]
10
GPQ1 [3:2] 00 = Input 01 = Output
10 = MEM0_CAS 11 = Ext. Interrupt Group9[1]
10
GPQ2 [5:4] 00 = Input 01 = Output
10 = MEM0_SCLK 11 = Ext. Interrupt Group9 [2]
10
GPQ3 [7:6] 00 = Input 01 = Output
10 = MEM0_SCLKn 11 = Ext. Interrupt Group9 [3]
10
GPQ4 [9:8] 00 = Input 01 = Output
10 = MEM0_SCKE 11 = Ext. Interrupt Group9 [4]
10
GPQ5 [11:10] 00 = Input 01 = Output
10 = MEM0_DQS[0] 11 = Ext. Interrupt Group9 [5]
10
GPQ6 [13:12] 00 = Input 01 = Output
10 = MEM0_DQS[1] 11 = Ext. Interrupt Group9 [6]
10
GPQ7 [15:14] 00 = Input 01 = Output
10 = MEM0_WEn_dmc 11 = Ext. Interrupt Group9 [7]
10
GPQ8 [17:16] 00 = Input 01 = Output
10 = MEM0_AP_dmc 11 = Ext. Interrupt Group9 [8]
10
GPQDAT Bit Description
GPQ[8:0] [8:0] When the port is configured as input port, the corresponding bit is the pin state.
When the port is configured as output port, the pin state is the same as the
corresponding bit. When the port is configured as functional pin, the undefined
value will be read.