Samsung S3C6400X, Руководство пользователя, Страница: 545 / 1189

PRELIMINARY
S3C6400X RISC MICROPROCESSOR GRAPHICS 2D
18-13
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
INTC_PEND_REG Bit Description
CLRSEL [31] Level interrupt & pulse interrupt mode select.
1 : level interrupt mode select(interrupt clear enable)
0: pulse interrupt mode select
Reserved [30:11]
INTP_DE_FIN [10] Graphics Drawing Engine finished.
INTP_FINISH_ALL [9] Graphics Engine IDLE state.
INTP_OVERFLOW [8] Overflow Interrupt.
Reserved [7:1]
INTP_FIFO_LEVEL [0] When FIFO_INT_LEVEL is same with FIFO_NO_USED, this bit will be set.
GENERAL FIFO STATUS REGISTER (FIFO_STAT_REG)
Register Offset R/W Description Reset Value
FIFO_STAT_REG 0x76100010 R Command FIFO Status register. 0x0000_0600
FIFO_STAT_REG Bit Description Initial State
Reserved [31:13] 0x0
DE_FIN [10] Graphics Drawing Engine finished. 1
G2D_IDLE [9] Graphics Engine IDLE state. 1
OVR_INT [8] Overflow Interrupt. 0
Reserved [7:6] 0x0
FIFO_NO_USED [5:0] The number of FIFO entry used. 0x0
GENERAL FRAME BUFFER BASE ADDRESS REGISTER (FB_BA_REG)
Register Offset R/W Description Reset Value
FB_BA_REG 0x76100020 R/W Frame Buffer Base Address register. 0x0000_0000
FB_BA_REG Bit Description Initial State
FrameBufAddr [31:10] The upper 22 bits of the frame buffer address. The 8 most significant
bits (MSB) determine the upper bound of the frame buffer. For
example, if user set the frame buffer address as 0x60800000, the
maximum memory allocation the frame buffer has is [0x60800000,
0x60FFFFFF]. 0x0
Reserved [9:0] The lowest 10 bits of the frame buffer address are set to 0 by force,
meaning the frame buffer address should be aligned to 1K bytes. 0x0