PRELIMINARY
ONENAND CONTROLLER
S3C6400X RISC MICROPROCESSOR
7-4
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
INPUT CLOCKS
The OneNAND controller has three clock source inputs. Bus system interface gets AHB bus clock, HCLK. Flash
controller core gets two flash clocks, mclk and mclk_flash. Frequency of mclk must be double of mclk_flash, which
is supplied to OneNAND flash memory.
You can set the frequency ratio in the SFR of the System Controller. Please refer
chapter 2 system controller
for
detailed information about clock ratio settings.
When you change the clock frequency ratio, you must follow the following procedure:
1. Ensure that there are no memory transfers.
2. Switch the clock ratio in the SFR of System Controller.
3. Write to the Clock Ratio Register.
4. Start the memory accesses.
MEMORY ADDRESS MAPPING
The OneNAND Controller reads the memory device’s dev_id size field to determine the address map and
automatically configures the MEM_ADDR field of the address map to support the device. Table 7-1 “MEM_ADDR
Fields” defines the field sizes for several OneNAND memory devices.
Table 7-1 MEM_ADDR Fields
MEM_ADDR Field
dev_id
size
field
Density
# of
Blocks
Page
Size
MAP
location
Reserved
DFS_DBS
FBA
FPA
FS
A
Reserved
0000 128Mb 256 1KB [23:22] [21:17]
N/A
[16:9]
[8:3] [2] [1:0]
0001 256Mb 512 1KB [23:22] [21:18]
N/A
[17:9]
[8:3] [2] [1:0]
0010 512Mb 512 2KB [23:22] [21:19]
N/A [18:10]
[9:4]
[3:2] [1:0]
0011
1Gb
Dual Die
1024 2KB [23:22]
[21:20] [19]
[18:10]
[9:4]
[3:2]
[1:0]
0011 1Gb 1024 2KB
[23:22] [21]
N/A [19:10]
[9:4]
[3:2] [1:0]
0100
2Gb
Dual Die
2048 2KB [23:22]
[21] [20]
[19:10]
[9:4]
[3:2]
[1:0]
0100 2Gb 2048 2KB
[23:22] N/A
N/A [20:10]
[9:4]
[3:2] [1:0]
0101
4Gb
Dual Die
4096 2KB [23:22]
N/A [21]
[20:10]
[9:4]
[3:2]
[1:0]
0101 4Gb 4096 2KB
[23:22] N/A
N/A [21:10]
[9:4]
[3:2] [1:0]