PRELIMINARY
DRAM CONTROLLER
S3C6400X RISC MICROPROCESSOR
5-14
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Read delay
[12:11]
Encodes the delay used when reading from the pad interface to
allow for de-skew of incoming read data
00 = Read delay 0 cycle (usually for SDR SDRAM)
01 = Read delay 1 cycle (usually for DDR SDRAM and mobile
DDR SDRAM)
10, 11 = Read delay 2 cycle
01
Memory type
[10:8]
The type of SDRAM that is attached to DRAM controller:
000 = SDR SDRAM
001 = DDR SDRAM
011 = mobile DDR SDRAM
010 = Embedded SDRAM
1xx = reserved
011
Memory width
[7:6]
The width of the external memory
00 = 16-bit
01 = 32-bit
10 = 64-bit
11 = 128-bit
00 / 01
Bank bits
[5:4]
Encodes the number of bit of the AXI address that comprise the
bank address.
00 = 2 bits
01 = 1 bit
10 = 0 bit
11 = reserved
00
Reserved
[3]
Read as Zero. Write as Zero.
0
DQM init
[2]
State of DQM when memory reset is de-asserted.
0
Clock config
[1:0]
The clock scheme supports:
00 = AXI clock and memory clock are asynchronous.
01 = AXI clock and memory clock are synchronous, and AXI clock
is the same frequency or slower than memory clock.
S3C6400X supports synchronous configuration. If this value is set
to asynchronous, S3C6400X should endure performance
degradation.
10~11 = reserved
00
ID_N_CFG REGISTER
Register
Address
R/W
Description
Reset Value
P0_id_0_cfg
~P0_id_15_cfg
0x7E000100
~0x7E00013C
R/W
16-bit DRAM controller id_<n>_cfg register
0x000
P1_id_0_cfg
~P1_id_15_cfg
0x7E001100
~0x7E00113C
R/W
32-bit DRAM controller id_<n>_cfg register
0x000