Samsung S3C6400X, Руководство пользователя, Страница: 29 / 1189

PRELIMINARY
PRODUCT OVERVIEW S3C6400 RISC MICROPROCESSOR
1-26
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
]
XspiMOSI[0] IO IO O I GPC[2] XspiMOSI[0] ADDR_CF[2]
EINT2[2
]
XspiCS[0] IO IO O I GPC[3] XspiCS[0]
EINT2[3
]
XspiMISO[1] IO IO IO O I GPC[4] XspiMISO[1] XmmcCMD2
EINT2[4
]
XspiCLK[1] IO IO O O I GPC[5] XspiCLK[1] XmmcCLK2
EINT2[5
]
XspiMOSI[1] IO IO O I GPC[6] XspiMOSI[1]
EINT2[6
]
XspiCS[1] IO IO O I GPC[7] XspiCS[1]
EINT2[7
]
Signal I/O Description
XspiMISO[0]
IO SPI MISO[0]. SPI master data input line
XspiCLK[0] IO SPI CLK[0]. SPI clock for channel 0
XspiMOSI[0]
IO SPI MOSI[0]. SPI master data output line
XspiCS[0] IO SPI chip select(only for slave mode)
XspiMISO[1] IO SPI MISO[1]. SPI master data input line
XspiCLK[1]
IO SPI CLK[1]. SPI clock for channel 1
XspiMOSI[1] IO SPI MOSI[1]. SPI master data output line
XspiCS[1] IO SPI chip select(only for slave mode)
ADDR_CF[2:0] O CF card address
EINT2[7:0] I External Interrupt 2
XmmcCMD2 IO COMMAND/RESPONSE (SD/SDIO/MMC card interface channel 2)
XmmcCLK2 O CLOCK (SD/SDIO/MMC card interface channel 2)
•
PCM(2-Ch) / IIS / AC97
I/O Function
Signal
0 1 2 3 4 5 6 0 1 2 3 4 5 6
XpcmDCLK[0]
O IO I O IO I XpcmDCLK[0] Xi2sCLK[0] X97BITCLK ADDR_CF[0] GPD[0] EINT3[0]
XpcmEXTCLK[0]
I O O O IO I XpcmEXTCLK[0] Xi2sCDCLK[0] X97RESETn ADDR_CF[1] GPD[1] EINT3[1]
XpcmFSYNC[0]
O IO O O IO I XpcmFSYNC[0] Xi2sLRCK[0] X97SYNC ADDR_CF[2] GPD[2] EINT3[2]
XpcmSIN[0]
I I I IO I
XpcmSIN[0]
Xi2sDI[0] X97SDI GPD[3] EINT3[3]
XpcmSOUT[0]
O O O IO I XpcmSOUT[0] Xi2sDO[0] X97SDO GPD[4] EINT3[4]
XpcmDCLK[1]
O IO I IO I XpcmDCLK[1] Xi2sCLK[1] X97BITCLK GPE[0]
XpcmEXTCLK[1]
I O O IO I XpcmEXTCLK[1] Xi2sCDCLK[1] X97RESETn GPE[1]