PRELIMINARY
DRAM CONTROLLER
S3C6400X RISC MICROPROCESSOR
5-8
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Active chips
[22:21]
Enables the refresh command generation for the number of memory
chips. It is only possible to generate commands up to and including
the number of chips in the configuration defined in the DRAM
controller status register:
00 = 1 chip
01 = 2 chips
10 = 3 chips
11 = 4 chips
00
QoS master bits
[20:18]
Encodes the four bits of the 8-bit AXI ARID that are used to select
one of the 16 QoS values:
000 = ARID[3:0]
001 = ARID[4:1]
010 = ARID[5:2]
011 = ARID[6:3]
100 = ARID[7:4]
101~111 = Reserved
000
Memory burst
[17:15]
Encodes the number of data accesses that are performed to the
SDRAM for each Read and Write command:
000 = Burst 1
001 = Burst 2
010 = Burst 4
011 = Burst 8
100 = Burst 16
101~111 = Reserved
This value must also be programmed into SDRAM mode register
using the DIRECTCMD register and must match it.
010
Stop_mem_clock [14]
When enabled the memory clock is dynamically stopped when not
performing an access to the SDRAM.
0
Auto power down
[13]
When Auto power down is set, the memory interface automatically
places the SDRAM into power-down state by de
-
asserting CKE
when the command FIFO has been empty for Power_down_prd
memory clock cycles.
0
Power_down_prd
[12:7]
Number of memory clock cycles for auto power-down of SDRAM.
000000
AP bit
[6]
Encodes the position of the auto-precharge bit in the memory
address:
0 = address bit 10.
1 = address bit 8.
0