Samsung S3C6400X, Руководство пользователя, Страница: 1121 / 1189

PRELIMINARY
IRDA S3C6400X RISC MICROPROCESSOR
38-14
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
IRDA INTERUPT ENALBLE REGISTER(IRDA_IER)
Register Address R/W Description Reset Value
IrDA _IER 0x7F00_700C R/W IrDA Interrupt Enable Register 0x00
IrDA_IER Bit Description Initial State
Last byte to Rx FIFO [7] Enables state indication interrupt. When Last byte write to
RX FIFO.
0
Error indication [6] Enables error status indication interrupt in data receiving
mode.
0
Tx Underrun [5] Enables transmitter under-run interrupt. 0
Last byte detect [4] Detect stop-flag interrupt enable. If this bit is set to “1”, an
interrupt signal will be activated when the last byte of the
received data frame comes into the demodulation block
and then CRC decoding is finished.
0
Rx overrun [3] Enables receiver over-run interrupt. 0
Last byte read from Rx
FIFO
[2] Bit 2 enables last byte from RX FIFO interrupt which is
generated when the microcontroller reads the last byte of
the frame from the RX FIFO.
0
Tx FIFO below
threshold
[1] Bit 1 enables an TX FIFO below threshold level interrupt
when the available empty space in TX FIFO is over the
threshold level.
0
Rx FIFO over threshold [0] Bit 0 enables received data in RX FIFO over threshold
level interrupt when the RX FIFO is equal to or above the
threshold level.
0